codeloc1k.tan.rpt

实现电子密码锁的各项功能,经过编译和仿真

; N/A           ; None        ; -5.361 ns ; q_temp[3] ; cnt10:inst5|c_temp[2]     ; clk4     ;
; N/A           ; None        ; -5.361 ns ; q_temp[3] ; cnt10:inst5|c_temp[1]     ; clk4     ;
; N/A           ; None        ; -5.361 ns ; q_temp[3] ; cnt10:inst5|c_temp[0]     ; clk4     ;
; N/A           ; None        ; -5.422 ns ; q_temp[4] ; cnt10:inst5|cout2         ; clk4     ;
; N/A           ; None        ; -5.422 ns ; q_temp[4] ; cnt10:inst5|c_temp[3]     ; clk4     ;
; N/A           ; None        ; -5.422 ns ; q_temp[4] ; cnt10:inst5|c_temp[2]     ; clk4     ;
; N/A           ; None        ; -5.422 ns ; q_temp[4] ; cnt10:inst5|c_temp[1]     ; clk4     ;
; N/A           ; None        ; -5.422 ns ; q_temp[4] ; cnt10:inst5|c_temp[0]     ; clk4     ;
; N/A           ; None        ; -5.500 ns ; q_temp[1] ; cnt10:inst5|cout2         ; clk4     ;
; N/A           ; None        ; -5.500 ns ; q_temp[1] ; cnt10:inst5|c_temp[3]     ; clk4     ;
; N/A           ; None        ; -5.500 ns ; q_temp[1] ; cnt10:inst5|c_temp[2]     ; clk4     ;
; N/A           ; None        ; -5.500 ns ; q_temp[1] ; cnt10:inst5|c_temp[1]     ; clk4     ;
; N/A           ; None        ; -5.500 ns ; q_temp[1] ; cnt10:inst5|c_temp[0]     ; clk4     ;
; N/A           ; None        ; -5.503 ns ; q_temp[6] ; cnt10:inst5|cout2         ; clk4     ;
; N/A           ; None        ; -5.503 ns ; q_temp[6] ; cnt10:inst5|c_temp[3]     ; clk4     ;
; N/A           ; None        ; -5.503 ns ; q_temp[6] ; cnt10:inst5|c_temp[2]     ; clk4     ;
; N/A           ; None        ; -5.503 ns ; q_temp[6] ; cnt10:inst5|c_temp[1]     ; clk4     ;
; N/A           ; None        ; -5.503 ns ; q_temp[6] ; cnt10:inst5|c_temp[0]     ; clk4     ;
; N/A           ; None        ; -5.804 ns ; clk2      ; cnt1:inst13|ccout         ; clk4     ;
; N/A           ; None        ; -6.679 ns ; clk2      ; cnt1:inst13|qqout[0]~reg0 ; clk4     ;
+---------------+-------------+-----------+-----------+---------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Dec 06 15:21:40 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off codeloc1k -c codeloc1k --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk4" is an undefined clock
    Info: Assuming node "clk2" is an undefined clock
    Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk4" has Internal fmax of 337.38 MHz between source register "cnt30:inst6|d_temp[1]" and destination register "cnt30:inst6|d_temp[0]" (period= 2.964 ns)
    Info: + Longest register to register delay is 2.762 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y15_N1; Fanout = 6; REG Node = 'cnt30:inst6|d_temp[1]'
        Info: 2: + IC(0.418 ns) + CELL(0.454 ns) = 0.872 ns; Loc. = LC_X1_Y15_N6; Fanout = 1; COMB Node = 'cnt30:inst6|LessThan~58'
        Info: 3: + IC(0.527 ns) + CELL(0.340 ns) = 1.739 ns; Loc. = LC_X1_Y15_N9; Fanout = 5; COMB Node = 'cnt30:inst6|d_temp[4]~4'
        Info: 4: + IC(0.356 ns) + CELL(0.667 ns) = 2.762 ns; Loc. = LC_X1_Y15_N0; Fanout = 4; REG Node = 'cnt30:inst6|d_temp[0]'
        Info: Total cell delay = 1.461 ns ( 52.90 % )
        Info: Total interconnect delay = 1.301 ns ( 47.10 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk4" to destination register is 2.271 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_153; Fanout = 13; CLK Node = 'clk4'
            Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X1_Y15_N0; Fanout = 4; REG Node = 'cnt30:inst6|d_temp[0]'
            Info: Total cell delay = 1.677 ns ( 73.84 % )
            Info: Total interconnect delay = 0.594 ns ( 26.16 % )
        Info: - Longest clock path from clock "clk4" to source register is 2.271 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_153; Fanout = 13; CLK Node = 'clk4'
            Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X1_Y15_N1; Fanout = 6; REG Node = 'cnt30:inst6|d_temp[1]'
            Info: Total cell delay = 1.677 ns ( 73.84 % )
            Info: Total interconnect delay = 0.594 ns ( 26.16 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: No valid register-to-register data paths exist for clock "clk2"
Info: No valid register-to-register data paths exist for clock "clk1"
Info: tsu for register "cnt1:inst13|qqout[0]~reg0" (data pin = "clk2", clock pin = "clk4") is 6.720 ns
    Info: + Longest pin to register delay is 8.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_173; Fanout = 10; CLK Node = 'clk2'
        Info: 2: + IC(6.587 ns) + CELL(0.225 ns) = 7.942 ns; Loc. = LC_X3_Y15_N9; Fanout = 1; COMB Node = 'inst10'
        Info: 3: + IC(0.353 ns) + CELL(0.667 ns) = 8.962 ns; Loc. = LC_X3_Y15_N2; Fanout = 1; REG Node = 'cnt1:inst13|qqout[0]~reg0'
        Info: Total cell delay = 2.022 ns ( 22.56 % )
        Info: Total interconnect delay = 6.940 ns ( 77.44 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk4" to destination register is 2.271 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_153; Fanout = 13; CLK Node = 'clk4'
        Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X3_Y15_N2; Fanout = 1; REG Node = 'cnt1:inst13|qqout[0]~reg0'
        Info: Total cell delay = 1.677 ns ( 73.84 % )
        Info: Total interconnect delay = 0.594 ns ( 26.16 % )
Info: tco from clock "clk2" to destination pin "fb" through register "Reg2:inst1|b[5]" is 16.776 ns
    Info: + Longest clock path from clock "clk2" to source register is 8.561 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_173; Fanout = 10; CLK Node = 'clk2'
        Info: 2: + IC(6.884 ns) + CELL(0.547 ns) = 8.561 ns; Loc. = LC_X2_Y18_N2; Fanout = 1; REG Node = 'Reg2:inst1|b[5]'
        Info: Total cell delay = 1.677 ns ( 19.59 % )
        Info: Total interconnect delay = 6.884 ns ( 80.41 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 8.042 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y18_N2; Fanout = 1; REG Node = 'Reg2:inst1|b[5]'
        Info: 2: + IC(0.402 ns) + CELL(0.454 ns) = 0.856 ns; Loc. = LC_X2_Y18_N4; Fanout = 1; COMB Node = 'compare8:inst3|reduce_nor~60'
        Info: 3: + IC(0.928 ns) + CELL(0.340 ns) = 2.124 ns; Loc. = LC_X3_Y15_N8; Fanout = 9; COMB Node = 'compare8:inst3|reduce_nor~63'
        Info: 4: + IC(0.365 ns) + CELL(0.225 ns) = 2.714 ns; Loc. = LC_X3_Y15_N4; Fanout = 1; COMB Node = 'compare8:inst3|fb~10'
        Info: 5: + IC(3.694 ns) + CELL(1.634 ns) = 8.042 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'fb'
        Info: Total cell delay = 2.653 ns ( 32.99 % )
        Info: Total interconnect delay = 5.389 ns ( 67.01 % )
Info: Longest tpd from source pin "clk7" to destination pin "police11" is 8.015 ns
    Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'clk7'
    Info: 2: + IC(1.561 ns) + CELL(0.225 ns) = 2.916 ns; Loc. = LC_X1_Y15_N8; Fanout = 1; COMB Node = 'police111:inst12|police11~16'
    Info: 3: + IC(3.465 ns) + CELL(1.634 ns) = 8.015 ns; Loc. = PIN_174; Fanout = 0; PIN Node = 'police11'
    Info: Total cell delay = 2.989 ns ( 37.29 % )
    Info: Total interconnect delay = 5.026 ns ( 62.71 % )
Info: th for register "Reg2:inst1|b[5]" (data pin = "q_temp[5]", clock pin = "clk2") is 3.531 ns
    Info: + Longest clock path from clock "clk2" to destination register is 8.561 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_173; Fanout = 10; CLK Node = 'clk2'
        Info: 2: + IC(6.884 ns) + CELL(0.547 ns) = 8.561 ns; Loc. = LC_X2_Y18_N2; Fanout = 1; REG Node = 'Reg2:inst1|b[5]'
        Info: Total cell delay = 1.677 ns ( 19.59 % )
        Info: Total interconnect delay = 6.884 ns ( 80.41 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 5.042 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'q_temp[5]'
        Info: 2: + IC(3.823 ns) + CELL(0.089 ns) = 5.042 ns; Loc. = LC_X2_Y18_N2; Fanout = 1; REG Node = 'Reg2:inst1|b[5]'
        Info: Total cell delay = 1.219 ns ( 24.18 % )
        Info: Total interconnect delay = 3.823 ns ( 75.82 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Dec 06 15:21:41 2007
    Info: Elapsed time: 00:00:01