codelock.tan.rpt

实现电子密码锁的各项功能,经过编译和仿真

; N/A           ; None        ; -1.597 ns ; q_temp[3] ; cnt10:inst5|c_temp[1] ; clk      ;
; N/A           ; None        ; -1.631 ns ; q_temp[1] ; cnt10:inst5|c_temp[3] ; clk      ;
; N/A           ; None        ; -1.631 ns ; q_temp[1] ; cnt10:inst5|c_temp[0] ; clk      ;
; N/A           ; None        ; -1.631 ns ; q_temp[1] ; cnt10:inst5|c_temp[2] ; clk      ;
; N/A           ; None        ; -1.631 ns ; q_temp[1] ; cnt10:inst5|c_temp[1] ; clk      ;
; N/A           ; None        ; -1.650 ns ; q_temp[0] ; cnt10:inst5|cout2     ; clk      ;
; N/A           ; None        ; -1.726 ns ; q_temp[4] ; cnt10:inst5|c_temp[3] ; clk      ;
; N/A           ; None        ; -1.726 ns ; q_temp[4] ; cnt10:inst5|c_temp[0] ; clk      ;
; N/A           ; None        ; -1.726 ns ; q_temp[4] ; cnt10:inst5|c_temp[2] ; clk      ;
; N/A           ; None        ; -1.726 ns ; q_temp[4] ; cnt10:inst5|c_temp[1] ; clk      ;
; N/A           ; None        ; -1.739 ns ; q_temp[5] ; cnt10:inst5|c_temp[3] ; clk      ;
; N/A           ; None        ; -1.739 ns ; q_temp[5] ; cnt10:inst5|c_temp[0] ; clk      ;
; N/A           ; None        ; -1.739 ns ; q_temp[5] ; cnt10:inst5|c_temp[2] ; clk      ;
; N/A           ; None        ; -1.739 ns ; q_temp[5] ; cnt10:inst5|c_temp[1] ; clk      ;
; N/A           ; None        ; -1.862 ns ; q_temp[0] ; cnt10:inst5|c_temp[3] ; clk      ;
; N/A           ; None        ; -1.862 ns ; q_temp[0] ; cnt10:inst5|c_temp[0] ; clk      ;
; N/A           ; None        ; -1.862 ns ; q_temp[0] ; cnt10:inst5|c_temp[2] ; clk      ;
; N/A           ; None        ; -1.862 ns ; q_temp[0] ; cnt10:inst5|c_temp[1] ; clk      ;
+---------------+-------------+-----------+-----------+-----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Dec 05 17:17:57 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off codelock -c codelock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 302.11 MHz between source register "Reg1:inst|a[6]" and destination register "cnt10:inst5|cout2" (period= 3.31 ns)
    Info: + Longest register to register delay is 3.108 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y20_N2; Fanout = 1; REG Node = 'Reg1:inst|a[6]'
        Info: 2: + IC(0.984 ns) + CELL(0.340 ns) = 1.324 ns; Loc. = LC_X2_Y17_N1; Fanout = 1; COMB Node = 'compare8:inst3|reduce_nor~67'
        Info: 3: + IC(0.343 ns) + CELL(0.454 ns) = 2.121 ns; Loc. = LC_X2_Y17_N9; Fanout = 8; COMB Node = 'compare8:inst3|reduce_nor~68'
        Info: 4: + IC(0.520 ns) + CELL(0.467 ns) = 3.108 ns; Loc. = LC_X1_Y17_N8; Fanout = 5; REG Node = 'cnt10:inst5|cout2'
        Info: Total cell delay = 1.261 ns ( 40.57 % )
        Info: Total interconnect delay = 1.847 ns ( 59.43 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 5.649 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X1_Y17_N8; Fanout = 5; REG Node = 'cnt10:inst5|cout2'
            Info: Total cell delay = 1.677 ns ( 29.69 % )
            Info: Total interconnect delay = 3.972 ns ( 70.31 % )
        Info: - Longest clock path from clock "clk" to source register is 5.649 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X2_Y20_N2; Fanout = 1; REG Node = 'Reg1:inst|a[6]'
            Info: Total cell delay = 1.677 ns ( 29.69 % )
            Info: Total interconnect delay = 3.972 ns ( 70.31 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "cnt10:inst5|c_temp[3]" (data pin = "q_temp[0]", clock pin = "clk") is 1.903 ns
    Info: + Longest pin to register delay is 7.523 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_1; Fanout = 2; PIN Node = 'q_temp[0]'
        Info: 2: + IC(3.929 ns) + CELL(0.454 ns) = 5.513 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; COMB Node = 'or88:inst2|qout~46'
        Info: 3: + IC(0.326 ns) + CELL(0.454 ns) = 6.293 ns; Loc. = LC_X1_Y17_N6; Fanout = 5; COMB Node = 'inst9'
        Info: 4: + IC(0.563 ns) + CELL(0.667 ns) = 7.523 ns; Loc. = LC_X2_Y17_N3; Fanout = 3; REG Node = 'cnt10:inst5|c_temp[3]'
        Info: Total cell delay = 2.705 ns ( 35.96 % )
        Info: Total interconnect delay = 4.818 ns ( 64.04 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 5.649 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X2_Y17_N3; Fanout = 3; REG Node = 'cnt10:inst5|c_temp[3]'
        Info: Total cell delay = 1.677 ns ( 29.69 % )
        Info: Total interconnect delay = 3.972 ns ( 70.31 % )
Info: tco from clock "clk" to destination pin "fb" through register "Reg1:inst|a[6]" is 14.707 ns
    Info: + Longest clock path from clock "clk" to source register is 5.649 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X2_Y20_N2; Fanout = 1; REG Node = 'Reg1:inst|a[6]'
        Info: Total cell delay = 1.677 ns ( 29.69 % )
        Info: Total interconnect delay = 3.972 ns ( 70.31 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 8.885 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y20_N2; Fanout = 1; REG Node = 'Reg1:inst|a[6]'
        Info: 2: + IC(0.984 ns) + CELL(0.340 ns) = 1.324 ns; Loc. = LC_X2_Y17_N1; Fanout = 1; COMB Node = 'compare8:inst3|reduce_nor~67'
        Info: 3: + IC(0.343 ns) + CELL(0.454 ns) = 2.121 ns; Loc. = LC_X2_Y17_N9; Fanout = 8; COMB Node = 'compare8:inst3|reduce_nor~68'
        Info: 4: + IC(0.966 ns) + CELL(0.225 ns) = 3.312 ns; Loc. = LC_X1_Y15_N1; Fanout = 1; COMB Node = 'compare8:inst3|fb~10'
        Info: 5: + IC(3.939 ns) + CELL(1.634 ns) = 8.885 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'fb'
        Info: Total cell delay = 2.653 ns ( 29.86 % )
        Info: Total interconnect delay = 6.232 ns ( 70.14 % )
Info: Longest tpd from source pin "clk6" to destination pin "police11" is 9.334 ns
    Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_153; Fanout = 1; PIN Node = 'clk6'
    Info: 2: + IC(2.884 ns) + CELL(0.225 ns) = 4.239 ns; Loc. = LC_X1_Y15_N0; Fanout = 1; COMB Node = 'inst12~76'
    Info: 3: + IC(3.461 ns) + CELL(1.634 ns) = 9.334 ns; Loc. = PIN_174; Fanout = 0; PIN Node = 'police11'
    Info: Total cell delay = 2.989 ns ( 32.02 % )
    Info: Total interconnect delay = 6.345 ns ( 67.98 % )
Info: th for register "Reg2:inst1|b[7]" (data pin = "q_temp[7]", clock pin = "clk") is 0.772 ns
    Info: + Longest clock path from clock "clk" to destination register is 5.649 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X1_Y17_N9; Fanout = 1; REG Node = 'Reg2:inst1|b[7]'
        Info: Total cell delay = 1.677 ns ( 29.69 % )
        Info: Total interconnect delay = 3.972 ns ( 70.31 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 4.889 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_12; Fanout = 2; PIN Node = 'q_temp[7]'
        Info: 2: + IC(3.521 ns) + CELL(0.238 ns) = 4.889 ns; Loc. = LC_X1_Y17_N9; Fanout = 1; REG Node = 'Reg2:inst1|b[7]'
        Info: Total cell delay = 1.368 ns ( 27.98 % )
        Info: Total interconnect delay = 3.521 ns ( 72.02 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 05 17:17:58 2007
    Info: Elapsed time: 00:00:01