📄 startup.lst
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ARM Macro Assembler Page 1
1 00000000 ;define the stack size
2 00000000 00000000
SVC_STACK_LEGTH
EQU 0
3 00000000 00000000
FIQ_STACK_LEGTH
EQU 0
4 00000000 00000100
IRQ_STACK_LEGTH
EQU 256
5 00000000 00000000
ABT_STACK_LEGTH
EQU 0
6 00000000 00000000
UND_STACK_LEGTH
EQU 0
7 00000000
8 00000000 00000080
NoInt EQU 0x80
9 00000000 00000040
NoFIQ EQU 0x40
10 00000000
11 00000000
12 00000000 00000010
USR32Mode
EQU 0x10
13 00000000 00000013
SVC32Mode
EQU 0x13
14 00000000 0000001F
SYS32Mode
EQU 0x1f
15 00000000 00000012
IRQ32Mode
EQU 0x12
16 00000000 00000011
FIQ32Mode
EQU 0x11
17 00000000
18 00000000 E002C014
PINSEL2 EQU 0xE002C014
19 00000000
20 00000000 ;/* Define the Bus Speed */
21 00000000 FFE00000
BCFG0 EQU 0xFFE00000 ;// Control Word of
BANK0 / CS0
22 00000000 FFE00004
BCFG1 EQU 0xFFE00004 ;// Control Word of
BANK1 / CS1
23 00000000 FFE00008
BCFG2 EQU 0xFFE00008 ;// Control Word of
BANK2 / CS2
24 00000000 FFE0000C
BCFG3 EQU 0xFFE0000C ;// Control Word of
BANK3 / CS3
25 00000000
26 00000000 00000000
BCFG_08DEF
EQU 0x00000000 ;// 8Bit Bus
ARM Macro Assembler Page 2
27 00000000 10000400
BCFG_16DEF
EQU 0x10000400 ;// 16Bit Bus
28 00000000 20000400
BCFG_32DEF
EQU 0x20000400 ;// 32Bit Bus
29 00000000
30 00000000
31 00000000 10001460
BCFG_FLASH
EQU (BCFG_16DEF | (0x00<<00) | (0x0
3<<05) | (0x02<<11))
;// For 90ns Flash
32 00000000 10001460
BCFG_PSRAM
EQU (BCFG_16DEF | (0x00<<00) | (0x0
3<<05) | (0x02<<11))
;// For 70ns PSRAM
33 00000000 1000FFEF
BCFG_CS2
EQU (BCFG_16DEF | (0x0f<<00) | (0x1
f<<05) | (0x1f<<11))
;// Blank
34 00000000 10001C61
BCFG_CS3
EQU (BCFG_16DEF | (0x01<<00) | (0x0
3<<05) | (0x03<<11))
;// For Peripheral
Equipment
35 00000000
36 00000000 IMPORT __use_no_semihosting_swi
37 00000000 IMPORT __use_two_region_memory
38 00000000
39 00000000
40 00000000
41 00000000 IMPORT FIQ_Exception
42 00000000 IMPORT __main
43 00000000 IMPORT TargetResetInit
44 00000000
45 00000000
46 00000000 EXPORT bottom_of_heap
47 00000000 EXPORT bottom_of_Stacks
48 00000000 EXPORT top_of_heap
49 00000000 EXPORT StackUsr
50 00000000
51 00000000 EXPORT Reset
52 00000000 EXPORT __user_initial_stackheap
53 00000000
54 00000000 CODE32
55 00000000 PRESERVE8
56 00000000 AREA vectors,CODE,READONLY
57 00000000 ENTRY
58 00000000
59 00000000 ;interrupt vectors
60 00000000 Reset
61 00000000 E59FF018 LDR PC, ResetAddr
62 00000004 E59FF018 LDR PC, UndefinedAddr
63 00000008 E59FF018 LDR PC, SWI_Addr
64 0000000C E59FF018 LDR PC, PrefetchAddr
ARM Macro Assembler Page 3
65 00000010 E59FF018 LDR PC, DataAbortAddr
66 00000014 B9205F80 DCD 0xb9205f80
67 00000018 E51FFFF0 LDR PC, [PC, #-0xff0]
68 0000001C E59FF018 LDR PC, FIQ_Addr
69 00000020
70 00000020 00000000
ResetAddr
DCD ResetInit
71 00000024 00000000
UndefinedAddr
DCD Undefined
72 00000028 00000000
SWI_Addr
DCD SoftwareInterrupt
73 0000002C 00000000
PrefetchAddr
DCD PrefetchAbort
74 00000030 00000000
DataAbortAddr
DCD DataAbort
75 00000034 00000000
Nouse DCD 0
76 00000038 00000000
IRQ_Addr
DCD 0
77 0000003C 00000000
FIQ_Addr
DCD FIQ_Handler
78 00000040
79 00000040
80 00000040 Undefined
81 00000040 EAFFFFFE B Undefined
82 00000044
83 00000044 SoftwareInterrupt
84 00000044 ; B SoftwareInterrupt
85 00000044
86 00000044 E3500004 CMP R0, #4
87 00000048 379FF100 LDRLO PC, [PC, R0, LSL #2]
88 0000004C E1B0F00E MOVS PC, LR
89 00000050
90 00000050 SwiFunction
91 00000050 00000000 DCD IRQDisable ;0
92 00000054 00000000 DCD IRQEnable ;1
93 00000058 00000000 DCD FIQDisable ;2
94 0000005C 00000000 DCD FIQEnable ;3
95 00000060
96 00000060 IRQDisable
97 00000060
98 00000060 E14F0000 MRS R0, SPSR
99 00000064 E3800080 ORR R0, R0, #NoInt
100 00000068 E161F000 MSR SPSR_c, R0
101 0000006C E1B0F00E MOVS PC, LR
102 00000070
103 00000070 IRQEnable
104 00000070
105 00000070 E14F0000 MRS R0, SPSR
106 00000074 E3C00080 BIC R0, R0, #NoInt
107 00000078 E161F000 MSR SPSR_c, R0
108 0000007C E1B0F00E MOVS PC, LR
ARM Macro Assembler Page 4
109 00000080
110 00000080 FIQDisable
111 00000080
112 00000080 E14F0000 MRS R0, SPSR
113 00000084 E3800040 ORR R0, R0, #NoFIQ
114 00000088 E161F000 MSR SPSR_c, R0
115 0000008C E1B0F00E MOVS PC, LR
116 00000090
117 00000090 FIQEnable
118 00000090
119 00000090 E14F0000 MRS R0, SPSR
120 00000094 E3C00040 BIC R0, R0, #NoFIQ
121 00000098 E161F000 MSR SPSR_c, R0
122 0000009C E1B0F00E MOVS PC, LR
123 000000A0
124 000000A0
125 000000A0
126 000000A0 PrefetchAbort
127 000000A0 EAFFFFFE B PrefetchAbort
128 000000A4
129 000000A4
130 000000A4 DataAbort
131 000000A4 EAFFFFFE B DataAbort
132 000000A8
133 000000A8
134 000000A8 FIQ_Handler
135 000000A8 E92D400F STMFD SP!, {R0-R3, LR}
136 000000AC EBFFFFFE BL FIQ_Exception
137 000000B0 E8BD400F LDMFD SP!, {R0-R3, LR}
138 000000B4 E25EF004 SUBS PC, LR, #4
139 000000B8
140 000000B8 InitStack
141 000000B8 E1A0000E MOV R0, LR
142 000000BC ;Build the SVC stack
143 000000BC E321F0D3 MSR CPSR_c, #0xd3
144 000000C0 E59FD080 LDR SP, StackSvc
145 000000C4 ;Build the IRQ stack
146 000000C4 E321F0D2 MSR CPSR_c, #0xd2
147 000000C8 E59FD07C LDR SP, StackIrq
148 000000CC ;Build the FIQ stack
149 000000CC E321F0D1 MSR CPSR_c, #0xd1
150 000000D0 E59FD078 LDR SP, StackFiq
151 000000D4 ;Build the DATAABORT stack
152 000000D4 E321F0D7 MSR CPSR_c, #0xd7
153 000000D8 E59FD074 LDR SP, StackAbt
154 000000DC ;Build the UDF stack
155 000000DC E321F0DB MSR CPSR_c, #0xdb
156 000000E0 E59FD070 LDR SP, StackUnd
157 000000E4 ;Build the SYS stack
158 000000E4 E321F0DF MSR CPSR_c, #0xdf
159 000000E8 E59FD06C LDR SP, =StackUsr
160 000000EC
161 000000EC E12FFF10 BX R0
162 000000F0
163 000000F0 ResetInit
164 000000F0 ;Initial extenal bus controller.
165 000000F0
166 000000F0 E59F0068 LDR R0, =PINSEL2
167 000000F4 IF :DEF: EN_CRP
ARM Macro Assembler Page 5
170 000000F4 E59F1068 LDR R1, =0x0f814914
171 000000F8 ENDIF
172 000000F8 E5801000 STR R1, [R0]
173 000000FC
174 000000FC E59F0064 LDR R0, =BCFG0
175 00000100 E59F1064 LDR R1, =BCFG_FLASH
176 00000104 E5801000 STR R1, [R0]
177 00000108
178 00000108 E59F0060 LDR R0, =BCFG1
179 0000010C E59F1058 LDR R1, =BCFG_PSRAM
180 00000110 E5801000 STR R1, [R0]
181 00000114
182 00000114 E59F0058 LDR R0, =BCFG2
183 00000118 E59F1058 LDR R1, =BCFG_CS2
184 0000011C E5801000 STR R1, [R0]
185 00000120
186 00000120 E59F0054 LDR R0, =BCFG3
187 00000124 E59F1054 LDR R1, =BCFG_CS3
188 00000128 E5801000 STR R1, [R0]
189 0000012C
190 0000012C EBFFFFE1 BL InitStack ;Initialize the sta
ck
191 00000130 EBFFFFFE BL TargetResetInit ;Initialize the
target board
192 00000134 ;Jump to the entry point of C program
193 00000134 EAFFFFFE B __main
194 00000138
195 00000138
196 00000138 __user_initial_stackheap
197 00000138 E59F0044 LDR r0,=bottom_of_heap
198 0000013C ; LDR r1,=StackUsr
199 0000013C E59F2044 LDR r2,=top_of_heap
200 00000140 E59F3044 LDR r3,=bottom_of_Stacks
201 00000144 E12FFF1E BX lr
202 00000148
203 00000148
204 00000148 FFFFFFFC
StackSvc
DCD SvcStackSpace + (SVC_STACK_LEGT
H - 1)* 4
205 0000014C 000003FC
StackIrq
DCD IrqStackSpace + (IRQ_STACK_LEGT
H - 1)* 4
206 00000150 FFFFFFFC
StackFiq
DCD FiqStackSpace + (FIQ_STACK_LEGT
H - 1)* 4
207 00000154 FFFFFFFC
StackAbt
DCD AbtStackSpace + (ABT_STACK_LEGT
H - 1)* 4
208 00000158 FFFFFFFC
StackUnd
DCD UndtStackSpace + (UND_STACK_LEG
TH - 1)* 4
209 0000015C
210 0000015C IF :DEF: EN_CRP
220 ENDIF
ARM Macro Assembler Page 6
221 0000015C
222 0000015C
223 0000015C 00000000
E002C014
0F814914
FFE00000
10001460
FFE00004
FFE00008
1000FFEF
FFE0000C
10001C61
00000000
00000000
00000000 AREA MyStacks, DATA, NOINIT, ALIGN=2
224 00000000 SvcStackSpace
SPACE SVC_STACK_LEGTH * 4
225 00000000 IrqStackSpace
SPACE IRQ_STACK_LEGTH * 4
226 00000400 FiqStackSpace
SPACE FIQ_STACK_LEGTH * 4 ;Stack spac
es for Fast Interru
pt reQuest Mode
227 00000400 AbtStackSpace
SPACE ABT_STACK_LEGTH * 4 ;Stack spac
es for Suspend Mode
228 00000400 UndtStackSpace
SPACE UND_STACK_LEGTH * 4 ;Stack spac
es for Undefined Mo
de
229 00000400
230 00000400
231 00000400 AREA Heap, DATA, NOINIT
232 00000000 bottom_of_heap
SPACE 1
233 00000001
234 00000001 AREA StackBottom, DATA, NOINIT
235 00000000 bottom_of_Stacks
SPACE 1
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