_primary.vhd

来自「Multiple Numbers Calculator (source code」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity ripple_adder27 is
    port(
        sum             : out    vl_logic_vector(26 downto 0);
        cout            : out    vl_logic;
        a               : in     vl_logic_vector(26 downto 0);
        b               : in     vl_logic_vector(26 downto 0);
        c_in            : in     vl_logic
    );
end ripple_adder27;