syn.tcl

Multiple Numbers Calculator (source code and LAB notes)

#======================================================
#
# Synopsys Synthesis Scripts (Design Vision dctcl mode)
#
#======================================================

#======================================================
#  Set Libraries
#======================================================
set search_path {. ./ \
                   ~iclabt01/UMC018_LIB/Synthesis \
                   /usr/synopsys/libraries/syn/ }
#                   /misc/RAID2/EDA/synopsys/syn_vV-2004.06-SP1/libraries/syn }

set link_library {* slow.db dw01.sldb dw02.sldb dw03.sldb dw04.sldb dw05.sldb}
set synthetic_library {standard.sldb dw01.sldb dw02.sldb dw03.sldb dw04.sldb dw05.sldb}
set target_library {slow.db}


#======================================================
#  Global Parameters
#======================================================
set DESIGN "TRIANGLE"
set CLK_period 10
set MAX_Delay 10 

#======================================================
#  Read RTL Code
#======================================================
read_verilog -rtl $DESIGN\.v
current_design $DESIGN


#======================================================
#  Global Setting
#======================================================


#======================================================
#  Set Design Constraints
#======================================================
set_max_delay $MAX_Delay -from [all_inputs] -to [all_outputs]

#======================================================
#  Optimization
#======================================================
uniquify
set_fix_multiple_port_nets -all -buffer_constants
compile_ultra

#======================================================
#  Output Reports 
#======================================================
report_timing >  $DESIGN\.timing
report_area >  $DESIGN\.area

#======================================================
#  Change Naming Rule
#======================================================
set bus_inference_style "%s\[%d\]"
set bus_naming_style "%s\[%d\]"
set hdlout_internal_busses true

change_names -hierarchy -rule verilog

define_name_rules name_rule -allowed "a-z A-Z 0-9 _" -max_length 255 -type cell
define_name_rules name_rule -allowed "a-z A-Z 0-9 _[]" -max_length 255 -type net
define_name_rules name_rule -map {{"\\*cell\\*" "cell"}}
change_names -hierarchy -rules name_rule


#======================================================
#  Output Results
#======================================================
set verilogout_higher_designs_first true
write -format verilog -output $DESIGN\_SYN.v -hierarchy
write_sdf -version 2.1 -context verilog -load_delay cell $DESIGN\_SYN.sdf
#======================================================
#  Finish and Quit
#======================================================
exit