📄 fs_sdmmc_dev.h
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#define SDMMC_RESP_TX_TYPE_R1 0x0 /* response transfer type is R1 */
#define SDMMC_RESP_TX_TYPE_R1B (0x1 << 9) /* response transfer type is R1b */
#define SDMMC_RESP_TX_TYPE_R2 (0x2 << 9) /* response transfer type is R2 */
#define SDMMC_RESP_TX_TYPE_R3 (0x3 << 9) /* response transfer type is R3 */
#define SDMMC_RESP_TX_TYPE_R6 (0x6 << 9) /* response transfer type is R6 */
/* Command and response transfer error status */
#define SDMMC_CMD_RESP_TX_STAT_N_ERR 0x0 /* command and response transfer error status is no error */
#define SDMMC_CMD_RESP_TX_STAT_ERR (0x1 << 8) /* command and response transfer error status is error */
/* SD commandu index */
#define SDMMC_CMD_INDEX(x) (x & 0x3F)
/*
* SDMMC_SD_CMDRES
* */
/* Card command transfer signal */
#define SDMMC_CARD_CMD_TX_SIGNAL_BEGIN (0x1 << 8) /* card command transfer begins */
#define SDMMC_CARD_RESP_TX_SIGNAL_BEGIN (0x1 << 7) /* card response transfer begins */
#define SDMMC_CARD_CMD_RESP_STAT_ERR (0x1 << 6) /* card command and response status is error */
#define SDMMC_CARD_CMD_RESP_BUS_CONFLICT_ERR (0x1 << 5) /* card command and response bus conflict is error */
#define SDMMC_CARD_RESP_TO_ERR (0x1 << 4) /* card response timeout is error */
#define SDMMC_CARD_RESP_TX_BIT_ERR (0x1 << 3) /* card response transmission bit is error */
#define SDMMC_CARD_RESP_IDX_ERR (0x1 << 2) /* card response index is error */
#define SDMMC_CARD_RESP_CRC_ERR (0x1 << 1) /* card response CRC is error */
#define SDMMC_CARD_RESP_END_BIT_ERR 0x1 /* card response end bit is error */
/*
* SDMMC_SD_DATAT
* */
/* Data transfer signal */
#define SDMMC_DATA_TX_SIGNAL_END 0x0 /* data transfer end */
#define SDMMC_DATA_TX_SIGNAL_BEGIN (0x1 << 13) /* data transfer begins */
/* Data transfer direction */
#define SDMMC_DATA_TX_DIR_READ 0x0 /* data transfer direction is read */
#define SDMMC_DATA_TX_DIR_WRITE (0x1 << 12) /* data transfer direction is write */
/* Data transfer bus width */
#define SDMMC_DATA_TX_BUS_WIDTH_LINE_1 0x0 /* data transfer bus width is line */
#define SDMMC_DATA_TX_BUS_WIDTH_LINE_4 (0x1 << 11) /* data transfer bus width is lines */
/* Data transfer with DMA function */
#define SDMMC_DATA_TX_DMA_DIS 0x0 /* disable data transfer with DMA function */
#define SDMMC_DATA_TX_DMA_EN (0x1 << 10) /* enable data transfer with DMA function */
/* Data transfer cycle */
#define SDMMC_DATA_TX_CYC_SINGLE 0x0 /* data transfer cycle is single */
#define SDMMC_DATA_TX_CYC_MULTIPLE (0x1 << 9) /* data transfer cycle is multiple */
/* Data transfer error */
#define SDMMC_DATA_TX_STAT_ERR (0x1 << 8) /* data transfer error status is error */
#define SDMMC_DATA_TX_BUS_CONFLICT_ERR (0x1 << 7) /* data transfer conflict error is error */
#define SDMMC_DATA_TX_TO_ERR (0x1 << 6) /* data transfer timeout error is error */
#define SDMMC_DATA_TX_CRC_ERR (0x1 << 5) /* data transfer CRC error is error */
#define SDMMC_READ_DATA_TX_STR_BIT_ERR (0x1 << 4) /* read data transfer start bit error is error */
#define SDMMC_READ_DATA_TX_END_BIT_ERR (0x1 << 3) /* read data transfer end bit error is error */
#define SDMMC_WRITE_DATA_TX_CRC_STAT_N_ERR 0x2 /* write data transfer CRC status is no error */
#define SDMMC_WRITE_DATA_TX_CRC_STAT_CRC_ERR 0x5 /* write data transfer CRC status is CRC error */
#define SDMMC_WRITE_DATA_TX_CRC_STAT_NO_RESP 0x7 /* write data transfer CRC status is no response */
#endif
/*
* Header for MultiMediaCard (MMC)
*
* Copyright 2002 Hewlett-Packard Company
*
* Use consistent with the GNU GPL is permitted,
* provided that this copyright notice is
* preserved in its entirety in all copies and derived works.
*
* HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
* FITNESS FOR ANY PARTICULAR PURPOSE.
*
* Many thanks to Alessandro Rubini and Jonathan Corbet!
*
* Based strongly on code by:
*
* Author: Yong-iL Joh <tolkien@mizi.com>
* Date : $Date: 2007/12/24 07:56:11 $
*
* Author: Andrew Christian
* 15 May 2002
*/
#ifndef MMC_MMC_PROTOCOL_H
#define MMC_MMC_PROTOCOL_H
/* Standard MMC commands (3.1) type argument response */
/* class 1 */
#define MMC_GO_IDLE_STATE 0 /* bc */
#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
#define MMC_ALL_SEND_CID 2 /* bcr R2 */
#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
#define MMC_SET_DSR 4 /* bc [31:16] RCA */
#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
/* class 2 */
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
/* class 3 */
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
/* class 4 */
#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
#define MMC_WRITE_SINGLE_BLOCK 24 /* adtc [31:0] data addr R1 */
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
#define MMC_PROGRAM_CID 26 /* adtc R1 */
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
/* class 6 */
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
/* SD's commands */
#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data address R1 */
#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data address R1 */
/* class 5 */
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
#define MMC_ERASE 38 /* ac R1b */
/* class 9 */
#define MMC_FAST_IO 39 /* ac <Complex> R4 */
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
/* class 7 */
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
/* class 8 */
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
/* SD commands type argument response */
/* class 8 */
/* This is basically the same command as for MMC with some quirks. */
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
/* Application commands */
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
#define SD_APP_SEND_SCR 51 /* adtc R1 */
/*
MMC status in R1
Type
e : error bit
s : status bit
r : detected and set for the actual command response
x : detected and set during command execution. the host must poll
the card by sending status command in order to read these bits.
Clear condition
a : according to the card state
b : always related to the previous command. Reception of
a valid command will clear it (with a delay of one command)
c : clear by read
*/
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
#define R1_CC_ERROR (1 << 20) /* erx, c */
#define R1_ERROR (1 << 19) /* erx, c */
#define R1_UNDERRUN (1 << 18) /* ex, c */
#define R1_OVERRUN (1 << 17) /* ex, c */
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
#define R1_ERASE_RESET (1 << 13) /* sr, c */
#define R1_STATUS(x) (x & 0xFFFFE000)
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
#define R1_APP_CMD (1 << 5) /* sr, c */
/*
* Interrupt Bit
* */
enum int_bit
{
CMD_RESP_INT = (1 << 2),
DATA_TX_INT = (1 << 1),
CARD_DET_INT = 1
};
#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */
#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */
#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */
#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */
#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */
#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */
#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */
#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
/*
* CSD field definitions
*/
#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */
#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */
/*
* SD bus widths
*/
#define SD_BUS_WIDTH_1 0
#define SD_BUS_WIDTH_4 2
/* SDHC 情况下使用的定义 */
#define SD_SET_WR_BLK_ERASE_COUNT 23 /* ACMD23 Pre erase */
#define SD_HC_SEND_IF_COND 8 /*CMD8*/
#define SDMMC_RESP_TX_TYPE_R7 SDMMC_RESP_TX_TYPE_R6 /* response transfer type is R7,暂时用R6来代替 */
#define HC_SD_CARD 2 /* Ver2.00 or later SD Memory Card */
#endif
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