fs_sdmmc_dev.h

瑞星微公司RK27XX系列芯片的SDK开发包

/*
$Log: fs_sdmmc_dev.h,v $
Revision 1.4  2007/12/24 07:56:11  Lingzhaojun
同步蓝魔版本基本模块

Revision 1.3  2007/10/16 07:14:46  Fangzhenfu
根据 RK27XX 进行修改！ 1 线读写，SD MMC 支持， 可支持 大小
端读写设置！

Revision 1.2  2007/10/08 02:57:43  Lingzhaojun
添加版本自动注释脚本

*/

#ifndef _SD_H_
#define _SD_H_

//1常量定义
#define  SUCCEED     0
#define  TIME_OUT 1
#define  NO_CARD     2


//1全局变量
#undef EXT
#ifdef _IN_SD_
#define EXT
#else
#define EXT  extern
#endif

extern const FS_DEVICE_TYPE FS_SdmmcDevice;

//1表格定义

/*************************************************************************************************/
/**                                                                                             **/
/**若检测脚有改变，需要注意同时修改以下SDMMC_CHK_GPIO和SDCheckInsetLevel两个宏                  **/
/**                                                                                             **/
/*************************************************************************************************/

#define     SDCheckInsetLevel   0    //SD卡插入时，若您所用的检测脚为低电平，则设置为0；否则设置为1

/*************************************************************************************************/


#define     SDMMC_ISR_PROC_EN   0
#define     SD_CARD             0
#define     MMC_CARD            1

#define READ_BLOCK_LEN_OFFSET       16
#define READ_BLOCK_LEN_MASK         0x000F0000
#define CSIZE_MULT_OFFSET           15
#define CSIZE_MULT_MASK             0x00038000


/* SD卡相关宏定义 */
#if(RK27XX_IO_MEMMAP == LDK_MMU_DISABLE)
#define SDMMC_ADDR_BASE     0x1E920000
#elif(RK27XX_IO_MEMMAP == LDK_MMU_ENABLE)
#define SDMMC_ADDR_BASE     0x03920000
#elif(RK27XX_IO_MEMMAP == PORSCHE9_IO_MEMMAP)
#define SDMMC_ADDR_BASE     0x18024000
#else
#undef SDMMC_ADDR_BASE
#endif


#define SDMMC_MMU_CTRL      (SDMMC_ADDR_BASE + 0x0000)
#define SDMMC_MMU_PNRI      (SDMMC_ADDR_BASE + 0x0004)
#define SDMMC_CUR_PNRI      (SDMMC_ADDR_BASE + 0x0008)
#define SDMMC_MMU_PNRII     (SDMMC_ADDR_BASE + 0x000C)
#define SDMMC_CUR_PNRII     (SDMMC_ADDR_BASE + 0x0010)
#define SDMMC_MMU_ADDR      (SDMMC_ADDR_BASE + 0x0014)
#define SDMMC_CUR_ADDR      (SDMMC_ADDR_BASE + 0x0018)
#define SDMMC_MMU_DATA      (SDMMC_ADDR_BASE + 0x001C)
#define SDMMC_SD_CTRL       (SDMMC_ADDR_BASE + 0x0020)
#define SDMMC_SD_INT        (SDMMC_ADDR_BASE + 0x0024)
#define SDMMC_SD_CARDA      (SDMMC_ADDR_BASE + 0x0028)
#define SDMMC_SD_CARDB      (SDMMC_ADDR_BASE + 0x002C)
#define SDMMC_SD_CMDREST    (SDMMC_ADDR_BASE + 0x0030)
#define SDMMC_SD_CMDRESA    (SDMMC_ADDR_BASE + 0x0034)
#define SDMMC_SD_CMDRESB    (SDMMC_ADDR_BASE + 0x0038)
#define SDMMC_SD_DATAT      (SDMMC_ADDR_BASE + 0x003C)
#define SDMMC_SD_CMD        (SDMMC_ADDR_BASE + 0x0040)
#define SDMMC_SD_RESA3      (SDMMC_ADDR_BASE + 0x0044)
#define SDMMC_SD_RESA2      (SDMMC_ADDR_BASE + 0x0048)
#define SDMMC_SD_RESA1      (SDMMC_ADDR_BASE + 0x004C)
#define SDMMC_SD_RESA0      (SDMMC_ADDR_BASE + 0x0050)
#define SDMMC_SD_RESB3      (SDMMC_ADDR_BASE + 0x0054)
#define SDMMC_SD_RESB2      (SDMMC_ADDR_BASE + 0x0058)
#define SDMMC_SD_RESB1      (SDMMC_ADDR_BASE + 0x005C)
#define SDMMC_SD_RESB0      (SDMMC_ADDR_BASE + 0x0060)


/*
 *  SDMMC_MMU_CTRL
 *  */
/* Endian control when CPU access to data buffer */
#define SDMMC_LITTLE_ENDIAN_ACCESS 0x0 /* Little endian access */
#define SDMMC_BIG_ENDIAN_ACCESS (0x1 << 12) /* Big endian access */

/* MMU DMA transfer signal */
#define SDMMC_MMU_DMA_TX_SIGNAL_END 0x0 /* MMU DMA transfer end */
#define SDMMC_MMU_DMA_TX_SIGNAL_BEGIN (0x1 << 11) /* MMU DMA transfer begin */

/* MMU DMA transfer direction */
#define SDMMC_MMU_DMA_TX_DIR_READ 0 /* MMU DMA transfer direction is read */
#define SDMMC_MMU_DMA_TX_DIR_WRITE (0x1 << 10) /* MMU DMA transfer direction is write */

/* MMU bus control swap data buffer */
#define SDMMC_MMU0_BUS_CTRL_DATABUF_1 0x0 /* the MMU0 bus control data buffer1 and the MMU1 bus control data buffer2 */
#define SDMMC_MMU0_BUS_CTRL_DATABUF_2 (0x1 << 9) /* the MMU1 bus control data buffer2 and the MMU1 bus control data buffer1 */

/* CPU control swap data buffer */
#define SDMMC_HOST_CTRL_DATABUF_1 0x0 /* the host microprocessor control data buffer1 */
#define SDMMC_HOST_CTRL_DATABUF_2 (0x1 << 8) /* the host microprocessor control data buffer2 */

/* Reset data buffer2 pointer */
#define SDMMC_DATABUF_2_POINTER_KEEP 0x0 /* keep data buffer2 pointer */
#define SDMMC_DATABUF_2_POINTER_RST (0x1 << 7) /* reset data buffer2 pointer and return 0 automatically */

/* Data buffer2 pointer and signal */
#define SDMMC_DATABUF_2_POINTER_END_SIGNAL_LOW 0x0 /* data buffer2 pointer end signal is low */
#define SDMMC_DATABUF_2_POINTER_END_SIGNAL_HIGH (0x1 << 6) /* data buffer2 pointer end signal is high */

/* Indicate data buffer2 transfer width */
#define SDMMC_DATABUF_2_TX_WIDTH_BYTE 0x0 /* data buffer2 transfer width is byte */
#define SDMMC_DATABUF_2_TX_WIDTH_HALFWORD (0x1 << 4) /* data bufffer2 transfer width is halfword */
#define SDMMC_DATABUF_2_TX_WIDTH_WORD (0x3 << 4) /* data buffer2 transfer width is word */

/* Reset data buffer1 pointer */
#define SDMMC_DATABUF_1_POINTER_KEEP 0x0 /* keep data buffer1 pointer */
#define SDMMC_DATABUF_1_POINTER_RST (0x1 << 3) /* reset data buffer1 pointer and return 0 automatically */

/* Data buffer1 pointer end signal */
#define SDMMC_DATABUF_1_POINTER_END_SIGNAL_LOW 0x0 /* data buffer1 pointer end signal is low */
#define SDMMC_DATABUF_1_POINTER_END_SINGAL_HIGH (0x1 << 2) /* data buffer1 pointer end signal is high */

/* Indicate data buffer1 transfer width */
#define SDMMC_DATABUF_1_TX_WIDTH_BYTE 0x0 /* data buffer1 transfer width is byte */
#define SDMMC_DATABUF_1_TX_WIDTH_HALFWORD 0x1 /* data buffer1 transfer width is halfword */
#define SDMMC_DATABUF_1_TX_WIDTH_WORD 0x3 /* data buffer1 transfer width is word */

#define SDMMC_MMU_DATA_WIDTH_BYTE (SDMMC_MMU_DMA_TX_SIGNAL_END | \
      SDMMC_MMU_DMA_TX_DIR_READ | \
      SDMMC_MMU0_BUS_CTRL_DATABUF_2 | \
      SDMMC_HOST_CTRL_DATABUF_1 | \
      SDMMC_DATABUF_2_POINTER_RST | \
      SDMMC_DATABUF_2_POINTER_END_SIGNAL_LOW | \
      SDMMC_DATABUF_2_TX_WIDTH_BYTE | \
      SDMMC_DATABUF_1_POINTER_RST | \
      SDMMC_DATABUF_1_POINTER_END_SIGNAL_LOW | \
      SDMMC_DATABUF_1_TX_WIDTH_BYTE)
#define SDMMC_MMU_DATA_WIDTH_HALFWORD (SDMMC_MMU_DMA_TX_SIGNAL_END | \
          SDMMC_MMU_DMA_TX_DIR_READ | \
          SDMMC_MMU0_BUS_CTRL_DATABUF_2 | \
          SDMMC_HOST_CTRL_DATABUF_1 | \
          SDMMC_DATABUF_2_POINTER_RST | \
          SDMMC_DATABUF_2_POINTER_END_SIGNAL_LOW | \
          SDMMC_DATABUF_2_TX_WIDTH_BYTE | \
          SDMMC_DATABUF_1_POINTER_RST | \
          SDMMC_DATABUF_1_POINTER_END_SIGNAL_LOW | \
          SDMMC_DATABUF_1_TX_WIDTH_HALFWORD)
#define SDMMC_MMU_DATA_WIDTH_WORD (SDMMC_MMU_DMA_TX_SIGNAL_END | \
      SDMMC_MMU_DMA_TX_DIR_READ | \
      SDMMC_MMU0_BUS_CTRL_DATABUF_2 | \
      SDMMC_HOST_CTRL_DATABUF_1 | \
      SDMMC_DATABUF_2_POINTER_RST | \
      SDMMC_DATABUF_2_POINTER_END_SIGNAL_LOW | \
      SDMMC_DATABUF_2_TX_WIDTH_BYTE | \
      SDMMC_DATABUF_1_POINTER_RST | \
      SDMMC_DATABUF_1_POINTER_END_SIGNAL_LOW | \
      SDMMC_DATABUF_1_TX_WIDTH_WORD)

/*
 *  SOCLE_MMU_ADDR
 *  */
#define SDMMC_SET_MMU_ADDR(x) ((x) & 0x00ffffff)

/*
 *  SDMMC_SD_CTRL
 *  */
/* Power control type for SD cards */
#define SDMMC_CARD_POWER_CTRL_CPU 0x0 /* the SD card power is controlled by CPU */
#define SDMMC_CARD_POWER_CTRL_CD (0x1 << 13) /* the SD card power is controlled by CD */

/* Card detect type for SD cards */
#define SDMMC_CARD_DETECT_FUNC_MECH 0x0 /* the card detect function is used by mechanism */
#define SDMMC_CARD_DETECT_FUNC_CDDAT3 (0x1 << 12) /* the card detect function is used by CD/DAT3 */

/* SD card clock stop register */
#define SDMMC_CARD_CLK_RUN 0x0 /* run the SD card clock */
#define SDMMC_CARD_CLK_STP (0x1 << 11) /* stop the SD card clock */

#define SDMMC_MAX_CLOCK_DIVIDER 0x000007FF

/* SD card clock divider register */
#define SDMMC_CARD_CLK_DIVIDER(x) (x & 0x7FF)

/*
 *  SDMMC_SD_INT
 *  */
/* Command and response transfer interrupt status */
#define SDMMC_CMD_RESP_TX_INT_STAT_NO     0x0         /* command and response transfer interrupt status is no */
#define SDMMC_CMD_RESP_TX_INT_STAT_YES    (0x1 << 6)  /* command and response transfer interrupt status is yes */

/* Data transfer interrupt status */
#define SDMMC_DATA_TX_INT_STAT_NO         0x0         /* data transfer interrupt status is no */
#define SDMMC_DATA_TX_INT_STAT_YES        (0x1 << 5)  /* data transfer interrupt status is yes */

/* Card detect interrupt status */
#define SDMMC_HOST_CARD_DETECT_INT_STAT_NO    0x0         /* card detect interrupt status is no */
#define SDMMC_HOST_CARD_DETECT_INT_STAT_YES   (0x1 << 4)  /* card detect interrupt status is yes */

/* Command and response transfer interrupt control */
#define SDMMC_CMD_RESP_TX_INT_DIS     0x0         /* disable command and response transfer interrupt */
#define SDMMC_CMD_RESP_TX_INT_EN      (0x1 << 2)  /* enable command and response transfer interrupt */

/* Data transfer interrupt control */
#define SDMMC_DATA_TX_INT_DIS         0x0         /* disable data transfer interrupt */
#define SDMMC_DATA_TX_INT_EN          (0x1 << 1)  /* enable data transfer interrupt */

/* card detect interrupt enable */
#define SDMMC_HOST_CARD_DETECT_INT_DIS 0x0 /* disable card detect interrupt */
#define SDMMC_HOST_CARD_DETECT_INT_EN 0x1 /* enable card detect interrupt */

/*
 *  SDMMC_SD_CARD
 *  */
/* Card select enable */
#define SDMMC_CARD_SEL_DIS 0x0 /* disable card select enable */
#define SDMMC_CARD_SEL_EN (0x1 << 6) /* enable card select */

/* Card power control signal */
#define SDMMC_CARD_POWER_CTRL_SIGNAL_DIS 0x0 /* disable card power control signal */
#define SDMMC_CARD_POWER_CTRL_SIGNAL_EN (0x1 << 5) /* enable card power control signal */

/* Card select interrupt enable */
#define SDMMC_CARD_DETECT_INT_DIS 0x0 /* disable card detect interrupt */
#define SDMMC_CARD_DETECT_INT_EN (0x1 << 4) /* enable card detect interrupt */

/* Card busy signal */
#define SDMMC_CARD_BUSY_SIGNAL_HIGH (0x1 << 2) /* card busy signal is high */

/* Card write protect signal */
#define SDMMC_CARD_WRITE_PROT_SIGNAL_HIGH (0x1 << 1) /* card write protect signal is high */

/* Card detect signal */
#define SDMMC_CARD_DETECT_SIGNAL_HIGH 0x1 /* card detect signal is high */

/*
 *  SDMMC_SD_CMDREST
 *  */
/* Command transfer signal */
#define SDMMC_CMD_TX_SIGNAL_END 0x0 /* command transfer end */
#define SDMMC_CMD_TX_SIGNAL_BEGIN (0x1 << 13) /* command transfer begins */

/* Response transfer signal */
#define SDMMC_RESP_TX_SIGNAL_END 0x0 /* response transfer end */
#define SDMMC_RESP_TX_SIGNAL_BEGIN (0x1 << 12) /* response transfer begins */

/* Response transfer type */