hal.c

瑞星微公司RK27XX系列芯片的SDK开发包

/********************************************************************
   COPYRIGHT (c)   2007 BY ROCK-CHIP FUZHOU
      --  ALL RIGHTS RESERVED  --
* File Name: UsbHal.c
* Author:  Oliver Miao
* Created:  2007-6-20 9:59
* Modified:
* Revision:  1.00
*
*********************************************************************
********************
* Module History
********************
*2007-6-20 10:10 Created by Oli
*2007-9-25 11:07    修改函数UsbWriteDataEP中对寄存器地址的取方式
                    例：(ChannelSet[0].uBulk_IN)--〉UDC_TX2STAT
*2007-9-25 11:13    修改函数UsbReadyToReadDataEP中对寄存器地址的取方式（同上）
*********************************************************************/
#include "hw_include.h"

#include "hw_common.h"
#include "usb.h"
#include "hw_memmap.h"
#include "BulkOnly.h"
#include "stdio.h"

//#define       USB11
UINT32 uControlDataSize;

/*__align(4) UINT8 g_pmid[16] =
{
    0x32,0x33, 0x44,0x45, 0x38,0x45, 0x32,0x41, 0x39,0x34,
    0x45,0x44, 0x43,0x43, 0x30,0x46
};
*/
extern  UINT8 *CtrlInBuffer  ;
extern BOOL bIsFullSpeed;

/********************************************************************
Routine  :  UDCInit
Input  :  None
Output  :  None
Function :  Called on first h/w init or reset
*********************************************************************/
void UDCInit()
{
#ifdef USB11
    // set UDC is Full-Speed mode, default is High-Speed mode
    WriteReg32(UDC_DEVCTL, ReadReg32(UDC_DEVCTL) | DEV_FULL_SPD);
#endif

    //WriteReg32(UDC_DEVCTL, ReadReg32(UDC_DEVCTL) & (~DEV_SOFT_CN));
    //WriteReg32( UDC_DEVCTL, (ReadReg32(UDC_DEVCTL)|DEV_SELF_PWR) );

    // init control endpoint
    WriteReg32(UDC_ENINT, EN_SETUP_INTR | EN_IN0_INTR | EN_OUT0_INTR | EN_BOUTALL_INTR |
               EN_BINALL_INTR | EN_IINALL_INTR | EN_USBRST_INTR | EN_RSUME_INTR |
               EN_SUSP_INTR);

    // level-trigger(default), high-active
    WriteReg32(UDC_INTCON, UDC_INTEN | UDC_INTHIGH_ACT);

    WriteReg32(UDC_TX0CON, TxACKINTEN | TxNAK);
    WriteReg32(UDC_RX0CON, RxACKINTEN | RxNAK |  RxEPEN);

    WriteReg32(UDC_RX1CON, (0x1 << 8) | RxACKINTEN  | RxEPEN);    //rx1con
    WriteReg32(UDC_TX2CON, (0x2 << 8) | TxDMADN_EN  | TxEPEN  | TxNAK | TxVOIDINTEN | TxERRINTEN);     //tx2con
}

/********************************************************************
Routine  :  UsbWriteCtlEP
Input  :  Data length & Data buffer
Output  :  Length that has been written
Function :  Write ctl endpoint fifo
*********************************************************************/
UINT32 UsbWriteCtlEP(UINT16 len, UINT8 * buf)
{
    int count, i;

#ifdef DEBUG
    serial_printf("WriteDataEndpoint \n");
#endif

    // dma done now, polling for empty data set
    //while(ReadReg32(UDC_TX0BUF) & TxFULL);
    for (i = 0; i < 0x100000; i++)
    {
        if (!(ReadReg32(UDC_TX0BUF) & TxFULL))
        {
            break;
        }
    }


    if (bIsFullSpeed)
    {
        count = (len >= FULL_SPEED_CTRL_PACKET_SIZE) ? FULL_SPEED_CTRL_PACKET_SIZE : len;  //oli 2007-6-1 21:02
    }
    else
    {
        count = (len >= HI_SPEED_CTRL_PACKET_SIZE) ? HI_SPEED_CTRL_PACKET_SIZE : len;  //oli 2007-6-1 21:02
    }

    uControlDataSize -= count;

    WriteReg32(UDC_TX0STAT, count);
    WriteReg32(UDC_DMA0LM_IADDR, virt_to_phy((UINT32)buf));
    WriteReg32(UDC_DMA0CTLI, ENP_DMA_START);

    CtrlInBuffer += count;

    // set ACK--after we have overwritten the previously incorrect data
    WriteReg32(UDC_TX0CON, ReadReg32(UDC_TX0CON) & ~TxNAK);

    return count;

}

/********************************************************************
Routine  :  UsbWriteDataEP
Input  :  Data length & Data buffer
Output  :  Length that has been written
Function :  Write data endpoint fifo (TX1)
*********************************************************************/
void UsbWriteDataEP(UINT16 len, UINT8 * buf)
{
    int i;
    int timeout = 100000;

    //while(ReadReg32(UDC_DMA2CTRLI)/*&0x01*/);
#ifdef DEBUG
    //printf("WriteDataEndpoint %x\n",len);
#endif

    // dma done now, polling for empty data set
    //while(ReadReg32(UDC_TX2BUF) & TxFULL);
    for (i = 0; i < 0x100000; i++)
    {
        if (!(ReadReg32(UDC_TX2BUF) & TxFULL))
        {
            break;
        }
    }
    /*
    if ( bIsFullSpeed )
    {
     count = (len>=FULL_SPEED_BULK_PACKET_SIZE)?FULL_SPEED_BULK_PACKET_SIZE:len;  //oli 2007-6-1 21:02
    }
    else
    {
     count = (len>=HI_SPEED_BULK_PACKET_SIZE)?HI_SPEED_BULK_PACKET_SIZE:len;  //oli 2007-6-1 21:02
    }
    */
    WriteReg32(UDC_TX2STAT/*(ChannelSet[0].uBulk_IN)*/, len);
    WriteReg32(UDC_DMA2LM_IADDR, virt_to_phy((UINT32)buf));
    WriteReg32(UDC_DMA2CTRLI, ENP_DMA_START);

    // set ACK--after we have overwritten the previously incorrect data
    WriteReg32(UDC_TX2CON, ReadReg32(UDC_TX2CON) & ~TxNAK);


    while (ReadReg32(UDC_DMA2CTRLI)&0x01)
    {
        if (!VBUS_OK())
            break;
        USDELAY(1);
        timeout --;
        if (0 == timeout)
            break;
    }

#if 0
    while (VBUS_OK())
    {
        if (!(ReadReg32(UDC_DMA2CTRLI)&0x01))
        {
            break;
        }
    }
#endif
    //return count;
}

/********************************************************************
Routine  :  UsbReadCtlEP
Input  :  Data length & Data buffer
Output  :  Void
Function :  Read control endpoint fifo
*********************************************************************/
void UsbReadyToReadCtlEP(UINT16 len, UINT8 * buf)
{
#if 0
    int count;

    if (bIsFullSpeed)
    {
        count = (len >= FULL_SPEED_CTRL_PACKET_SIZE) ? FULL_SPEED_CTRL_PACKET_SIZE : len;  //oli 2007-6-1 21:02
    }
    else
    {
        count = (len >= HI_SPEED_CTRL_PACKET_SIZE) ? HI_SPEED_CTRL_PACKET_SIZE : len;  //oli 2007-6-1 21:02
    }

    if ((len) != 0)
    {
        WriteReg32(UDC_DMA1LM_OADDR/*UDC_DMALM_OADDR(ChannelSet[0].uBulk_OUT)*/, virt_to_phy((UINT32)buf));
        WriteReg32(UDC_DMA1CTRLO/*UDC_DMACTRLI(ChannelSet[0].uBulk_OUT)*/, ENP_DMA_START);

        // set ACK--after we have overwritten the previously incorrect data
        //WriteReg32( UDC_TXCON(ChannelSet[endp].uBulk_IN) , ReadReg32(UDC_TXCON(ChannelSet[endp].uBulk_IN) ) & ~TxNAK);
    }
#endif
}

/********************************************************************
Routine  :  UsbReadyToReadDataEP
Input  :  Data buffer
Output  :  Void
Function :  Read data endpoint fifo
*********************************************************************/
void UsbReadyToReadDataEP(UINT8 * buf)
{
    WriteReg32(UDC_DMA1LM_OADDR, virt_to_phy((UINT32)buf));
    WriteReg32(UDC_DMA1CTRLO, ENP_DMA_START);
}

void UsbEnableRX()
{
    WriteReg32(UDC_RX0CON, ReadReg32(UDC_RX0CON) & ~RxNAK);
    WriteReg32(UDC_DMA0LM_OADDR, virt_to_phy((UINT32)CtrlInBuffer));
    WriteReg32(UDC_DMA0CTLO, ENP_DMA_START);
}