udcreg.h

瑞星微公司RK27XX系列芯片的SDK开发包

#define DEV_RESUME   (1<<5)
#define DEV_PHY16BIT  (1<<6)
#define SOFT_POR   (1<<7)
#define CSR_DONE   (1<<8)

/* UDC_DEVINFO */
#define DEV_ADDR   (0x0000007f) // Device address's bits mask
#define DEV_EN    (0x00000080) // Device enable bit mask
#define CFG_NUM    (0x00000f00) // Configuration number bits mask
#define IF_NUM    (0x0000f000) // Interface number bits mask
#define ALT_NUM    (0x000f0000) // Alternate setting number bits mask
#define VBUS_STS   (0x00100000) // VBUS status bit mask
#define ENUM_SPEED_MASK  (0x00600000) // Enum speed bits mask
#define ENUM_FULL_SPEED  (0x00600000) // FULL speed value
#define ENUM_HIGH_SPEED  (0x00000000) // HIGH speed value

/* UDC_ENINT */
#define EN_SOF_INTR   (1<<0)  /* Receive Start-Of-Frame Interrupt */
#define EN_SETUP_INTR  (1<<1)  /* Receive SETUP package */
#define EN_IN0_INTR   (1<<2)  /* ENP 0  Ctrl_IN  Transmit interrupt */
#define EN_OUT0_INTR  (1<<3)  /* ENP 0  Ctrl_OUT Receive interrupt  */
#define EN_USBRST_INTR  (1<<4)  /* USB Reset   Interrupt */
#define EN_RSUME_INTR  (1<<5)  /* USB Resume  Interrupt */
#define EN_SUSP_INTR  (1<<6)  /* USB Suspend Interrupt */

#define EN_ENP1_INTR  (1<<8)  /* ENP 1  Bulk_OUT Receive Interrupt  */
#define EN_ENP2_INTR  (1<<9)  /* ENP 2  Bulk_IN  Transmit Interrupt */
#define EN_ENP3_INTR  (1<<10)  /* ENP 3  Intr_IN  Transmit Interrupt */
#define EN_ENP4_INTR  (1<<11)  /* ENP 4  Bulk_OUT Receive Interrupt  */
#define EN_ENP5_INTR  (1<<12)  /* ENP 5  Bulk_IN  Transmit Interrupt */
#define EN_ENP6_INTR  (1<<13)  /* ENP 6  Intr_IN  Transmit Interrupt */
#define EN_ENP7_INTR  (1<<14)  /* ENP 7  Bulk_OUT Receive Interrupt  */
#define EN_ENP8_INTR  (1<<15)  /* ENP 8  Bulk_IN  Transmit Interrupt */
#define EN_ENP9_INTR  (1<<16)  /* ENP 9  Intr_IN  Transmit Interrupt */
#define EN_ENP10_INTR  (1<<17)  /* ENP 10 Bulk_OUT Receive Interrupt  */
#define EN_ENP11_INTR  (1<<18)  /* ENP 11 Bulk_IN  Transmit Interrupt */
#define EN_ENP12_INTR  (1<<19)  /* ENP 12 Intr_IN  Transmit Interrupt */
#define EN_ENP13_INTR  (1<<20)  /* ENP 13 Bulk_OUT Receive Interrupt  */
#define EN_ENP14_INTR  (1<<21)  /* ENP 14 Bulk_IN  Transmit Interrupt */
#define EN_ENP15_INTR  (1<<22)  /* ENP 15 Intr_IN  Transmit Interrupt */
#define EN_BOUTALL_INTR  (EN_ENP1_INTR | EN_ENP4_INTR | EN_ENP7_INTR | EN_ENP10_INTR | EN_ENP13_INTR)
#define EN_BINALL_INTR  (EN_ENP2_INTR | EN_ENP5_INTR | EN_ENP8_INTR | EN_ENP11_INTR | EN_ENP14_INTR)
#define EN_IINALL_INTR  (EN_ENP3_INTR | EN_ENP6_INTR | EN_ENP9_INTR | EN_ENP12_INTR | EN_ENP15_INTR)

/* UDC_INTFLG */
#define SOF_INTR   (1<<0)  /* Receive Start-Of-Frame Interrupt */
#define SETUP_INTR   (1<<1)  /* Receive SETUP package */
#define IN0_INTR   (1<<2)  /* ENP 0  Ctrl_IN  Transmit interrupt */
#define OUT0_INTR   (1<<3)  /* ENP 0  Ctrl_OUT Receive interrupt  */
#define USBRST_INTR   (1<<4)  /* USB Reset   Interrupt */
#define RSUME_INTR   (1<<5)  /* USB Resume  Interrupt */
#define SUSP_INTR   (1<<6)  /* USB Suspend Interrupt */
#define VBUS_INTR   (1<<7)  /* USB VBUS    Interrupt */

#define ENP1_INTR   (1<<8)  /* ENP 1  Bulk_OUT Receive Interrupt  */
#define ENP2_INTR   (1<<9)  /* ENP 2  Bulk_IN  Transmit Interrupt */
#define ENP3_INTR   (1<<10)  /* ENP 3  Intr_IN  Transmit Interrupt */
#define ENP4_INTR   (1<<11)  /* ENP 4  Bulk_OUT Receive Interrupt  */
#define ENP5_INTR   (1<<12)  /* ENP 5  Bulk_IN  Transmit Interrupt */
#define ENP6_INTR   (1<<13)  /* ENP 6  Intr_IN  Transmit Interrupt */
#define ENP7_INTR   (1<<14)  /* ENP 7  Bulk_OUT Receive Interrupt  */
#define ENP8_INTR   (1<<15)  /* ENP 8  Bulk_IN  Transmit Interrupt */
#define ENP9_INTR   (1<<16)  /* ENP 9  Intr_IN  Transmit Interrupt */
#define ENP10_INTR   (1<<17)  /* ENP 10 Bulk_OUT Receive Interrupt  */
#define ENP11_INTR   (1<<18)  /* ENP 11 Bulk_IN  Transmit Interrupt */
#define ENP12_INTR   (1<<19)  /* ENP 12 Intr_IN  Transmit Interrupt */
#define ENP13_INTR   (1<<20)  /* ENP 13 Bulk_OUT Receive Interrupt  */
#define ENP14_INTR   (1<<21)  /* ENP 14 Bulk_IN  Transmit Interrupt */
#define ENP15_INTR   (1<<22)  /* ENP 15 Intr_IN  Transmit Interrupt */

/* UDC_INTCON */
#define UDC_INTEN   (1<<0)  /* UDC Interrupt Enable bit */
#define UDC_INTEDGE_TRIG (1<<1)  /* UDC Interrupt Edge Trig bit */
#define UDC_INTHIGH_ACT  (1<<2)  /* UDC Interrupt Active High Trig bit */

/* UDC_SETUP1 */

/* UDC_SETUP2 */


/* Bulk-OUT End Point Define */

/* RXSTAT (Bulk_OUT, Read-Only) */
#define RxCNT    (0x7ff)  /* Bulk_OUT DMA Receive Count Mask */
#define RxVOID    (1<<16)  /* Bulk_OUT Stall Status bit */
#define RxERR    (1<<17)  /* Bulk_OUT DMA Receive Error bit */
#define RxACK    (1<<18)  /* Bulk_OUT Bus get ACK (transaction was successful) */
#define RxFULL    (1<<24)  /* Bulk_OUT Data Buffer Status, 1 -> buffer full */
#define RxOVF    (1<<25)  /* Bulk_OUT Receive Overflow */

/* RXCON (Bulk_OUT) */
#define RxCLR    (1<<1)  /* Bulk_OUT Flush FIFO */
#define RxSTALL    (1<<2)  /* Bulk_OUT Stall */
#define RxNAK    (1<<3)  /* Bulk_OUT Response NACK */
#define RxEPEN    (1<<4)  /* Bulk_OUT Enable */
#define RxVOIDINTEN   (1<<5)  /* Bulk_OUT Voild Interrupt Enable */
#define RxERRINTEN   (1<<6)  /* Bulk_OUT Error Interrupt Enable */
#define RxACKINTEN   (1<<7)  /* Bulk_OUT Receive ACK Interrupt Enable */
#define RxENPNUM   (0x0f00) /* Bulk_OUT ENP Number Mask */

/* Bulk-IN End Point Define */
/* Intr_IN End Point Define */

/* TXSTAT (Bulk_IN) */
#define TxCNT    (0x7ff)  /* Bulk_IN DMA Transmit Count Mask */
#define TxVOID    (1<<16)  /* Bulk_IN Stall Status bit */
#define TxERR    (1<<17)  /* Bulk_IN DMA Transmit Error bit */
#define TxACK    (1<<18)  /* Bulk_IN Bus get ACK (transaction was successful) */
#define TxDMADN    (1<<19)  /* Bulk_IN DMA transmit complete */

/* TXCON (Bulk_IN) */
#define TxCLR    (1<<0)  /* Bulk_IN Flush FIFO */
#define TxSTALL    (1<<1)  /* Bulk_IN Stall */
#define TxNAK    (1<<2)  /* Bulk_IN Response NACK */
#define TxEPEN    (1<<3)  /* Bulk_IN Enable */
#define TxVOIDINTEN   (1<<4)  /* Bulk_IN Voild Interrupt Enable */
#define TxERRINTEN   (1<<5)  /* Bulk_IN Error Interrupt Enable */
#define TxACKINTEN   (1<<6)  /* Bulk_IN Receive ACK Interrupt Enable */
#define TxDMADN_EN   (1<<7)  /* Bulk_IN DMA Enable */
#define TxENPNUM   (0x0f00) /* Bulk_IN ENP Number Mask */

/* TXBUF (Bulk_IN, Read-Only) */
#define TxFULL    (1<<0)  /* Bulk_IN Data Buffer Status, 1 -> buffer full */
#define TxURF    (1<<1)  /* Bulk_IN Transmit Underflow */
#define TxDS0    (1<<2)  /* Bulk_IN Data Set 0 Status bit, 1 -> buffer full */
#define TxDS1    (1<<3)  /* Bulk_IN Data Set 1 Status bit, 1 -> buffer full */

/* DMA Status Bit Mask */
#define ENP_DMASTATUS  (1<<0)
#define ENP_DMA_START  (1<<0)

/* register macro */
#define RETRIEVE_COUNT(x) ((x) & 0x7ff)

/* ivan 040803 */

/* For SET_UDC20_HIGH_SPEED */
// #define SET_UDC20_HIGH_SPEED
//#ifdef SET_UDC20_HIGH_SPEED
#define CTL_MAX_PKT            0x40
#define BULK_PKT_LSB           0x00
#define BULK_PKT_MSB           0x02
#define INTRIN_PKT_LSB         0x20
#define INTRIN_PKT_MSB         0x00
//#else
//     #define CTL_MAX_PKT            0x40
#define FS_BULK_PKT_LSB        0x40
#define FS_BULK_PKT_MSB        0x00
//     #define FS_INTRIN_PKT_LSB      0x20
//     #define FS_INTRIN_PKT_MSB      0x00
//#endif

/* Endpoint number Config SET 1*/
#define BLKOUT_ENDP_NUM_SET1     0x0d
#define BLKIN_ENDP_NUM_SET1      0x8e
#define INTRIN_ENDP_NUM_SET1     0x8f

/* Endpoint number Config SET 2*/
#define BLKOUT_ENDP_NUM_SET2     0x04
#define BLKIN_ENDP_NUM_SET2      0x85
#define INTRIN_ENDP_NUM_SET2     0x86

/* Endpoint number Config SET 3*/
#define BLKOUT_ENDP_NUM_SET3     0x07
#define BLKIN_ENDP_NUM_SET3      0x88
#define INTRIN_ENDP_NUM_SET3     0x89

/* Endpoint number Config SET 4*/
#define BLKOUT_ENDP_NUM_SET4     0x0a
#define BLKIN_ENDP_NUM_SET4      0x8b
#define INTRIN_ENDP_NUM_SET4     0x8c

/* Endpoint number Config SET 5*/
#define BLKOUT_ENDP_NUM_SET5     0x01
#define BLKIN_ENDP_NUM_SET5      0x82
#define INTRIN_ENDP_NUM_SET5     0x83
/* end of ivan 040803 */

#endif /* _UDC_REG_H_ */