udcreg.h

瑞星微公司RK27XX系列芯片的SDK开发包

/********************************************************************
   COPYRIGHT (c)   2007 BY ROCK-CHIP FUZHOU
      --  ALL RIGHTS RESERVED  --
* File Name: UdcReg.h
* Author:  Oliver Miao
* Created:  2007-6-20 16:29
* Modified:
* Revision:  1.00
*
*********************************************************************
********************
* Module History
********************
*2007-6-20 16:30 Creater by Oli
*********************************************************************/
#ifndef _UDC_REG_H_
#define _UDC_REG_H_

#include "hw_memmap.h"

/* UDC Registers Offset Define */
#define UDC_BASE    AHB0_UDC_BASE

#define PHY_TEST_EN   (UDC_BASE + 0x0000)  /* PHY. Enable Register (option) */
#define PHY_TEST   (UDC_BASE + 0x0004)  /* USB  PHY. Test Register (option) */
#define UDC_DEVCTL   (UDC_BASE + 0x0008)  /* Device Control Register */
#define UDC_DEVINFO   (UDC_BASE + 0x0010)  /* Device Info. Register */
#define UDC_ENINT   (UDC_BASE + 0x0014)  /* UDC Interrupt Enable Register */
#define UDC_INTFLG   (UDC_BASE + 0x0018)  /* UDC Interrupt Flag Register */
#define UDC_INTCON   (UDC_BASE + 0x001c)  /* UDC Interrupt Control Register */
#define UDC_SETUP1   (UDC_BASE + 0x0020)  /* UDC Setup Status Register 1 (Read-Only) */
#define UDC_SETUP2   (UDC_BASE + 0x0024)  /* UDC Setup Status Register 2 (Read-Only) */
#define UDC_AHBCON   (UDC_BASE + 0x0028)  /* UDC AHB Control Register */
/* ----------------------------------------- */
/* End-Point 0, Ctrl_OUT */
#define UDC_RX0STAT   (UDC_BASE + 0x0030)  /* UDC ENP 0 Ctrl_OUT Receive Status Register */
#define UDC_RX0CON   (UDC_BASE + 0x0034)  /* UDC ENP 0 Ctrl_OUT Receive Control Register */
#define UDC_DMA0CTLO  (UDC_BASE + 0x0038)  /* UDC ENP 0 Ctrl_OUT DMA Control Register */
#define UDC_DMA0LM_OADDR (UDC_BASE + 0x003c)  /* UDC ENP 0 Ctrl_OUT DMA Local Memory Address Register */
/* End-Point 0, Ctrl_IN */
#define UDC_TX0STAT   (UDC_BASE + 0x0040)  /* UDC ENP 0 Ctrl_IN Transmit Status Register */
#define UDC_TX0CON   (UDC_BASE + 0x0044)  /* UDC ENP 0 Ctrl_IN Transmit Control Register */
#define UDC_TX0BUF   (UDC_BASE + 0x0048)  /* UDC ENP 0 Ctrl_IN Buffer Status Register */
#define UDC_DMA0CTLI  (UDC_BASE + 0x004c)  /* UDC ENP 0 Ctrl_IN DMA Control Register */
#define UDC_DMA0LM_IADDR (UDC_BASE + 0x0050)  /* UDC ENP 0 Ctrl_IN DMA Local Memory Address Register */
/* ----------------------------------------- */
/* End-Point 1, Bulk_OUT */
#define UDC_RX1STAT   (UDC_BASE + 0x0054)  /* UDC ENP 1 Bulk_OUT Receive Status Register */
#define UDC_RX1CON   (UDC_BASE + 0x0058)  /* UDC ENP 1 Bulk_OUT Receive Control Register */
#define UDC_DMA1CTRLO  (UDC_BASE + 0x005c)  /* UDC ENP 1 Bulk_OUT DMA Control Register */
#define UDC_DMA1LM_OADDR (UDC_BASE + 0x0060)  /* UDC ENP 1 Bulk_OUT DMA Local Memory Address Register */
/* End-Point 2, Bulk_IN */
#define UDC_TX2STAT   (UDC_BASE + 0x0064)  /* UDC ENP 2 Bulk_IN Transmit Status Register */
#define UDC_TX2CON   (UDC_BASE + 0x0068)  /* UDC ENP 2 Bulk_IN Transmit Control Register */
#define UDC_TX2BUF   (UDC_BASE + 0x006c)  /* UDC ENP 2 Intr_IN Buffer Status Register */
#define UDC_DMA2CTRLI  (UDC_BASE + 0x0070)  /* UDC ENP 2 Bulk_IN DMA Control Register */
#define UDC_DMA2LM_IADDR (UDC_BASE + 0x0074)  /* UDC ENP 2 Bulk_IN DMA Local Memory Address Register */
/* End-Point 3, Intr_IN */
#define UDC_TX3STAT   (UDC_BASE + 0x0078)  /* UDC ENP 3 Intr_IN Transmit Status Register */
#define UDC_TX3CON   (UDC_BASE + 0x007c)  /* UDC ENP 3 Intr_IN Transmit Control Register */
#define UDC_TX3BUF   (UDC_BASE + 0x0080)  /* UDC ENP 3 Intr_IN Buffer Status Register */
#define UDC_DMA3CTRLI  (UDC_BASE + 0x0084)  /* UDC ENP 3 Intr_IN DMA Control Register */
#define UDC_DMA3LM_IADDR (UDC_BASE + 0x0088)  /* UDC ENP 3 Intr_IN DMA Local Memory Address Register */
/* ----------------------------------------- */
/* End-Point 4, Bulk_OUT */
#define UDC_RX4STAT   (UDC_BASE + 0x008c)  /* UDC ENP 4 Bulk_OUT Receive Status Register */
#define UDC_RX4CON   (UDC_BASE + 0x0090)  /* UDC ENP 4 Bulk_OUT Receive Control Register */
#define UDC_DMA4CTRLO  (UDC_BASE + 0x0094)  /* UDC ENP 4 Bulk_OUT DMA Control Register */
#define UDC_DMA4LM_OADDR (UDC_BASE + 0x0098)  /* UDC ENP 4 Bulk_OUT DMA Local Memory Address Register */
/* End-Point 5, Bulk_IN */
#define UDC_TX5STAT   (UDC_BASE + 0x009c)  /* UDC ENP 5 Bulk_IN Transmit Status Register */
#define UDC_TX5CON   (UDC_BASE + 0x00a0)  /* UDC ENP 5 Bulk_IN Transmit Control Register */
#define UDC_TX5BUF   (UDC_BASE + 0x00a4)  /* UDC ENP 5 Intr_IN Buffer Status Register */
#define UDC_DMA5CTRLI  (UDC_BASE + 0x00a8)  /* UDC ENP 5 Bulk_IN DMA Control Register */
#define UDC_DMA5LM_IADDR (UDC_BASE + 0x00ac)  /* UDC ENP 5 Bulk_IN DMA Local Memory Address Register */
/* End-Point 6, Intr_IN */
#define UDC_TX6STAT   (UDC_BASE + 0x00b0)  /* UDC ENP 6 Intr_IN Transmit Status Register */
#define UDC_TX6CON   (UDC_BASE + 0x00b4)  /* UDC ENP 6 Intr_IN Transmit Control Register */
#define UDC_TX6BUF   (UDC_BASE + 0x00b8)  /* UDC ENP 6 Intr_IN Buffer Status Register */
#define UDC_DMA6CTRLI  (UDC_BASE + 0x00bc)  /* UDC ENP 6 Intr_IN DMA Control Register */
#define UDC_DMA6LM_IADDR (UDC_BASE + 0x00c0)  /* UDC ENP 6 Intr_IN DMA Local Memory Address Register */
/* ----------------------------------------- */
/* End-Point 7, Bulk_OUT */
#define UDC_RX7STAT   (UDC_BASE + 0x00c4)  /* UDC ENP 7 Bulk_OUT Receive Status Register */
#define UDC_RX7CON   (UDC_BASE + 0x00c8)  /* UDC ENP 7 Bulk_OUT Receive Control Register */
#define UDC_DMA7CTRLO  (UDC_BASE + 0x00cc)  /* UDC ENP 7 Bulk_OUT DMA Control Register */
#define UDC_DMA7LM_OADDR (UDC_BASE + 0x00d0)  /* UDC ENP 7 Bulk_OUT DMA Local Memory Address Register */
/* End-Point 8, Bulk_IN */
#define UDC_TX8STAT   (UDC_BASE + 0x00d4)  /* UDC ENP 8 Bulk_IN Transmit Status Register */
#define UDC_TX8CON   (UDC_BASE + 0x00d8)  /* UDC ENP 8 Bulk_IN Transmit Control Register */
#define UDC_TX8BUF   (UDC_BASE + 0x00dc)  /* UDC ENP 8 Intr_IN Buffer Status Register */
#define UDC_DMA8CTRLI  (UDC_BASE + 0x00e0)  /* UDC ENP 8 Bulk_IN DMA Control Register */
#define UDC_DMA8LM_IADDR (UDC_BASE + 0x00e4)  /* UDC ENP 8 Bulk_IN DMA Local Memory Address Register */
/* End-Point 9, Intr_IN */
#define UDC_TX9STAT   (UDC_BASE + 0x00e8)  /* UDC ENP 9 Intr_IN Transmit Status Register */
#define UDC_TX9CON   (UDC_BASE + 0x00ec)  /* UDC ENP 9 Intr_IN Transmit Control Register */
#define UDC_TX9BUF   (UDC_BASE + 0x00f0)  /* UDC ENP 9 Intr_IN Buffer Status Register */
#define UDC_DMA9CTRLI  (UDC_BASE + 0x00f4)  /* UDC ENP 9 Intr_IN DMA Control Register */
#define UDC_DMA9LM_IADDR (UDC_BASE + 0x00f8)  /* UDC ENP 9 Intr_IN DMA Local Memory Address Register */
/* ----------------------------------------- */
/* End-Point 10, Bulk_OUT */
#define UDC_RX10STAT  (UDC_BASE + 0x00fc)  /* UDC ENP 10 Bulk_OUT Receive Status Register */
#define UDC_RX10CON   (UDC_BASE + 0x0100)  /* UDC ENP 10 Bulk_OUT Receive Control Register */
#define UDC_DMA10CTRLO  (UDC_BASE + 0x0104)  /* UDC ENP 10 Bulk_OUT DMA Control Register */
#define UDC_DMA10LM_OADDR (UDC_BASE + 0x0108)  /* UDC ENP 10 Bulk_OUT DMA Local Memory Address Register */
/* End-Point 11, Bulk_IN */
#define UDC_TX11STAT  (UDC_BASE + 0x010c)  /* UDC ENP 11 Bulk_IN Transmit Status Register */
#define UDC_TX11CON   (UDC_BASE + 0x0110)  /* UDC ENP 11 Bulk_IN Transmit Control Register */
#define UDC_TX11BUF   (UDC_BASE + 0x0114)  /* UDC ENP 11 Intr_IN Buffer Status Register */
#define UDC_DMA11CTRLI  (UDC_BASE + 0x0118)  /* UDC ENP 11 Bulk_IN DMA Control Register */
#define UDC_DMA11LM_IADDR (UDC_BASE + 0x011c)  /* UDC ENP 11 Bulk_IN DMA Local Memory Address Register */
/* End-Point 12, Intr_IN */
#define UDC_TX12STAT  (UDC_BASE + 0x0120)  /* UDC ENP 12 Intr_IN Transmit Status Register */
#define UDC_TX12CON   (UDC_BASE + 0x0124)  /* UDC ENP 12 Intr_IN Transmit Control Register */
#define UDC_TX12BUF   (UDC_BASE + 0x0128)  /* UDC ENP 12 Intr_IN Buffer Status Register */
#define UDC_DMA12CTRLI  (UDC_BASE + 0x012c)  /* UDC ENP 12 Intr_IN DMA Control Register */
#define UDC_DMA12LM_IADDR (UDC_BASE + 0x0130)  /* UDC ENP 12 Intr_IN DMA Local Memory Address Register */
/* ----------------------------------------- */
/* End-Point 13, Bulk_OUT */
#define UDC_RX13STAT  (UDC_BASE + 0x0134)  /* UDC ENP 13 Bulk_OUT Receive Status Register */
#define UDC_RX13CON   (UDC_BASE + 0x0138)  /* UDC ENP 13 Bulk_OUT Receive Control Register */
#define UDC_DMA13CTRLO  (UDC_BASE + 0x013c)  /* UDC ENP 13 Bulk_OUT DMA Control Register */
#define UDC_DMA13LM_OADDR (UDC_BASE + 0x0140)  /* UDC ENP 13 Bulk_OUT DMA Local Memory Address Register */
/* End-Point 14, Bulk_IN */
#define UDC_TX14STAT  (UDC_BASE + 0x0144)  /* UDC ENP 14 Bulk_IN Transmit Status Register */
#define UDC_TX14CON   (UDC_BASE + 0x0148)  /* UDC ENP 14 Bulk_IN Transmit Control Register */
#define UDC_TX14BUF   (UDC_BASE + 0x014c)  /* UDC ENP 14 Intr_IN Buffer Status Register */
#define UDC_DMA14CTRLI  (UDC_BASE + 0x0150)  /* UDC ENP 14 Bulk_IN DMA Control Register */
#define UDC_DMA14LM_IADDR (UDC_BASE + 0x0154)  /* UDC ENP 14 Bulk_IN DMA Local Memory Address Register */
/* End-Point 15, Intr_IN */
#define UDC_TX15STAT  (UDC_BASE + 0x0158)  /* UDC ENP 15 Intr_IN Transmit Status Register */
#define UDC_TX15CON   (UDC_BASE + 0x015c)  /* UDC ENP 15 Intr_IN Transmit Control Register */
#define UDC_TX15BUF   (UDC_BASE + 0x0160)  /* UDC ENP 15 Intr_IN Buffer Status Register */
#define UDC_DMA15CTRLI  (UDC_BASE + 0x0164)  /* UDC ENP 15 Intr_IN DMA Control Register */
#define UDC_DMA15LM_IADDR (UDC_BASE + 0x0168)  /* UDC ENP 15 Intr_IN DMA Local Memory Address Register */

/* Bulk_OUT, Receive End Point */
#define UDC_RXSTAT(x)  (x + 0x00)    /* UDC Bulk_OUT Receive Status Register */
#define UDC_RXCON(x)  (x + 0x04)    /* UDC Bulk_OUT Receive Control Register */
#define UDC_DMACTRLO(x)  (x + 0x08)    /* UDC Bulk_OUT DMA Control Register */
#define UDC_DMALM_OADDR(x) (x + 0x0c)    /* UDC Bulk_OUT DMA Local Memory Address Register */
/* Bulk_IN, Transmit End Point */
/* Intr_IN, Interrupt Transfer End Point */
#define UDC_TXSTAT(x)  (x + 0x00)    /* Bulk_IN/Intr_IN Transmit Status Register */
#define UDC_TXCON(x)  (x + 0x04)    /* Bulk_IN/Intr_IN Transmit Control Register */
#define UDC_TXBUF(x)  (x + 0x08)    /* Bulk_IN/Intr_IN Buffer Status Register */
#define UDC_DMACTRLI(x)  (x + 0x0c)    /* Bulk_IN/Intr_IN DMA Control Register */
#define UDC_DMALM_IADDR(x) (x + 0x10)    /* Bulk_IN/Intr_IN DMA Local Memory Address Register */

/* Bulk_OUT, Receive End Point */
#define RXSTAT(x)   (x + 0x00)    /* Bulk_OUT Receive Status Register */
#define RXCON(x)   (x + 0x04)    /* Bulk_OUT Receive Control Register */
#define DMACTRLO(x)   (x + 0x08)    /* Bulk_OUT DMA Control Register */
#define DMALM_OADDR(x)  (x + 0x0c)    /* Bulk_OUT DMA Local Memory Address Register */
/* Bulk_IN, Transmit End Point */
#define TXSTAT(x)   (x + 0x10)    /* Bulk_IN Transmit Status Register */
#define TXCON(x)   (x + 0x14)    /* Bulk_IN Transmit Control Register */
#define TXBUF(x)   (x + 0x18)    /* Intr_IN Buffer Status Register */
#define DMACTRLI(x)   (x + 0x1c)    /* Bulk_IN DMA Control Register */
#define DMALM_IADDR(x)  (x + 0x20)    /* Bulk_IN DMA Local Memory Address Register */
/* Intr_IN, Interrupt Transfer End Point */
#define INT_TXSTAT(x)  (x + 0x24)    /* Intr_IN Transmit Status Register */
#define INT_TXCON(x)  (x + 0x28)    /* Intr_IN Transmit Control Register */
#define INT_TXBUF(x)  (x + 0x2c)    /* Intr_IN Buffer Status Register */
#define INT_DMACTRLI(x)  (x + 0x30)    /* Intr_IN DMA Control Register */
#define INT_DMALM_IADDR(x) (x + 0x34)    /* Intr_IN DMA Local Memory Address Register */

/* PHY_TEST_EN */
#define PHY_TEST_CLK_EN  (1<<0) /* For Socle's PHY Test clock enable */
#define PHY_TEST_CLK  (1<<1) /* Enable Socle's PHY analog_test pin  */

/* PHY_TEST */    /* For Socle's PHY Test mode use */
#define PHY_TEST_ADDR  0x00
#define PHY_TEST_DATA_IN 0x04

/* UDC_DEVCTL */
#define DEV_FULL_SPD  (0x03) // Full speed (USB 1.1) define
#define DEV_SPEED   (0x00)
#define DEV_RMTWKP   (1<<2)
#define DEV_SELF_PWR  (1<<3)
#define DEV_SOFT_CN   (1<<4)