hw_i2c.h

瑞星微公司RK27XX系列芯片的SDK开发包

/******************************************************************/
/*   Copyright (C) 2007 ROCK-CHIPS FUZHOU . All Rights Reserved.  */
/*******************************************************************
File :  i2c.h
Desc :  定义I2C的寄存器结构体\寄存器位的宏定义\接口函数

Author : huangxinyu
Date : 2007-05-31
Notes :

$Log: hw_i2c.h,v $
Revision 1.5  2008/01/18 08:29:34  Lingzhaojun
no message

Revision 1.4  2008/01/12 11:20:37  Huangxinyu
TV-Out调试后的I2C优化,timeout处理与I2C Speed关联

Revision 1.3  2007/10/08 02:38:44  Lingzhaojun
添加版本自动注释脚本

*********************************************************************/
#ifndef _I2C_H
#define _I2C_H

/********************************************************************
 INCLUDE FILES
*********************************************************************/
#include "typedef.h"
#include "..\hwintr\hw_interrupt.h"
#include "hw_memmap.h"

/********************************************************************
 GLOBAL MACROS DEFINE
********************************************************************/
#define I2C_REG_BASE  APB0_I2C_BASE

// Interrupt status bit
#define I2C_INT_MACK (1<<0)   //Master receives ACK interrupt status bit
#define I2C_INT_MACKP (1<<1)   //Master ACK period interrupt status bit
#define I2C_INT_SACK (1<<2)   //Slave receives ACK interrupt status bit
#define I2C_INT_SACKP (1<<3)   //Slave ACK period interrupt status bit
#define I2C_INT_SAM  (1<<4)   //Slave address matches status bit
#define I2C_INT_SBA  (1<<5)   //Broadcast address 
#define I2C_INT_SAS  (1<<6)   //Abnormal stop occurs
#define I2C_INT_AL  (1<<7)   //Arbitration Lost

// I2C operation bit
#define I2C_OPR_DIV_SPEED_MASK   0x3F
#define I2C_OPR_ENABLE   (1<<6)       //I2C core enable bit
#define I2C_OPR_RESET   (1<<7)       //I2C state machine (both master/slave) reset bit
#define I2C_OPR_S10ADDR   (1<<8)       //Slave 10 bits address mode
#define I2C_OPR_S7ADDR   (0<<8)       //Slave 10 bits address mode

//I2C control register
#define I2C_LCMR_START (1<<0)
#define I2C_LCMR_STOP (1<<1)
#define I2C_LCMR_RESUME (1<<2)

//I2C line status register
#define I2C_LSR_BUSY (1<<0)   //I2C core busy status bit
#define I2C_LSR_NACK (1<<1)   //I2C receives NACK status bit

// I2C operation mode bit
#define I2C_CON_MASTER_TX   (3<<2)
#define I2C_CON_MASTER_RX  (1<<2)
#define I2C_CON_ACK             (0<<4)   //I2C bus acknowledge enable register
#define I2C_CON_NACK         (1<<4)   //I2C bus acknowledge enable register
#define I2C_CONR_MASTER_MASK (3<<2)
#define I2C_CONR_MRX (1<<2)   //Master receive mode
#define I2C_CONR_MTX (3<<2)   //Master transmit mode

#define I2C_CON_MASTER_TX   (3<<2)
#define I2C_CON_MASTER_RX  (1<<2)

#define I2C_READ_BIT    (1)
#define I2C_WRITE_BIT    (0)

#define I2C_10ADDR_PREFIX  (0x1e)

#if 0
#define I2C_SLAVEADDR_MASK      0x0000FF00
#define I2C_SPEED_MASK          0xFFFF0000
#define I2C_MODE_MASK           0x000000FF
#define I2C_GET_SLAVEADD(conf)      (((conf) & I2C_SLAVEADDR_MASK) >> 8)
#define I2C_GET_SPEED(conf)         (((conf) & I2C_SPEED_MASK) >> 16)
#define I2C_GET_MODE(conf)          ((conf) & I2C_MODE_MASK)
#endif
/*********************************************************************
 ENUMERATIONS AND STRUCTURES
*********************************************************************/
typedef volatile struct I2CReg
{
    REG32 I2C_MTXR;   // 0x00
    REG32 I2C_MRXR;   // 0x04
    REG32 I2C_STXR;   // 0x08
    REG32 I2C_SRXR;   // 0x0C
    REG32 I2C_SADDR;  // 0x10
    REG32 I2C_IER;    // 0x14
    REG32 I2C_ISR;    // 0x18
    REG32 I2C_LCMR;   // 0x1C
    REG32 I2C_LSR;    // 0x20
    REG32 I2C_CONR;   // 0x24
    REG32 I2C_OPR;    // 0x28
}I2CReg_t, *pI2CReg_t;


#endif /* _I2C_H */

/*********************************************************************
 END OF FILE
*********************************************************************/