hw_spi.h

瑞星微公司RK27XX系列芯片的SDK开发包

/******************************************************************/
/*   Copyright (C) 2007 ROCK-CHIPS FUZHOU . All Rights Reserved.  */
/*******************************************************************
File :  spi.h
Desc :  定义SPI的寄存器结构体\寄存器位的宏定义\接口函数

Author : huangxinyu
Date : 2007-06-01
Notes :

$Log: hw_spi.h,v $
Revision 1.3  2007/10/17 02:00:57  Huangxinyu
增加spi接口

Revision 1.2  2007/10/08 02:38:50  Lingzhaojun
添加版本自动注释脚本

*********************************************************************/
#ifndef _SPI_H
#define _SPI_H

/********************************************************************
 INCLUDE FILES
*********************************************************************/
#include "hw_include.h"

/********************************************************************
 GLOBAL MACROS DEFINE
*********************************************************************/
#define SPI_IS_RUNNING                  0x60000000 + 0x800000

#define SPI_BUFFER_BASE_ADDR            0x60810000

// location of uart transmit buffer
#define SPI_TX_BUFFER_SIZE              8192
#define SPI_TX_BUFFER_ADDR              SPI_BUFFER_BASE_ADDR
// location of uart receive buffer
#define SPI_RX_BUFFER_SIZE              8192
#define SPI_RX_BUFFER_ADDR              SPI_TX_BUFFER_ADDR+SPI_RX_BUFFER_SIZE

// Transcation flow control
#define LOOPBACK_ENABLE   0x0001  // Enable internal loopback mode
#define BIDIRECTION_ENABLE  0x0002  // Enable bidirection mode
#define LSB_FIRST_EN   0x0004  // Enable LSB first mode
#define CLOCK_PHASE    0x0008  // Select clock phase
#define CLOCK_POLARITY   0x0010  // Select clock polarity
#define CONCURRENT_ENABLE  0x0020  // Tx & Rx concurrent mode enable
#define CLOCK_IDLE_ASSERT  0x0100  // SPI clock idle enable control
#define SPI_RUN     0x0200  // SPI transmit & receive control, set this bit will start SPI controller /* SPI master core run */
#define MASETR_ENABLE   0x0400  // Enable master mode
#define RESET_CONTROL   0x0800  // Reset SPI controller

// FIFO control
#define SPI_FIFO_SIZE           8

#define SPI_TX_THRESH_2         (0<<8)
#define SPI_TX_THRESH_4         (1<<8)
#define SPI_TX_THRESH_6         (2<<8)
#define SPI_RX_THRESH_2         (0<<11)
#define SPI_RX_THRESH_4         (1<<11)
#define SPI_RX_THRESH_6         (2<<11)

#define RECEIVE_DATA_AVAILABLE  0x0001  // when this bit is set, there at last one data in receive FIFO
#define TRANSMIT_FIFO_FULL      0x0002  // when this bit is set, there transmit FIFO is full
#define CLEAR_TRANSMIT          0x0004  // clear transmit FIFO
#define CLEAR_RECEIVE           0x0008  // clear receive FIFO
#define TRANSMIT_LEVEL_MASK     0x0700//0x0070  // transimt FIFO level mask
#define RECEIVE_LEVEL_MASK      0x3800//0x0380  // receive FIFO level mask

// Interrupt enable control
#define TRANSFER_COMPLETE       0x0001  // transfer complete interrupt control
#define RECEIVE_FIFO_OVERRUN    0x0002  // receive FIFO overrun interrupt control
#define RECEIVE_DATA            0x0004  // receive FIFO level reach interrupt control
#define TRANSMIT_DATA           0x0008  // transmit FIFO level reach interrupt control

#define IE_RXCP                 0x0001  // transfer complete interrupt control
#define IE_OR                   0x0002  // receive FIFO overrun interrupt control
#define IE_RX                   0x0004  // receive FIFO level reach interrupt control
#define IE_TX                   0x0008  // transmit FIFO level reach interrupt control

// Clock delay control
#define ACTIVE_DELAY_MASK       0x0007      // Period before SPI clock active (PBCA).
#define TRANSFER_DELAY_MASK     0x0031      // Period between two consecutive transfer (PBCT).
#define TxRx_DELAY_MASK         0x0700      // Period between Tx and Rx transfer (PBTxRx).

#define CLOCK_HALF              0x00        // 1/2 clock
#define CLOCK_ZERO              0x00        // zero clock
#define CLOCK_4                 0x01        // 4 clock
#define CLOCK_8                 0x02        // 8 clock
#define CLOCK_16                0x03        // 16 clock
#define CLOCK_32                0x04        // 32 clock
#define CLOCK_64                0x05        // 64 clock
#define CLOCK_128               0x06        // 128 clock
#define CLOCK_256               0x07        // 256 clock

// slave select & characteristic control
#define CLOCK_DIVISOR_MASK      0x001f
#define SLAVE_SELECT_MASK       0x0700
#define CHARACTER_LENGTH_MASK   0x7800

// interrupt status
#define TRANSFER_COMPLETE_INT 0x01    // transfer complete interrupt
#define OVERRUN_INT             0x02    // overrun interrupt
#define RECEIVE_FIFO_INT        0x04    // receive FIFO level reach interrupt
#define TRANSMIT_FIFO_INT       0x08    // transmit FIFO level reach interrupt

// Config SPI flow control register
#if 0

// define
#define MSB_FIRST    0
#define LSB_FIRST    1

#define SPI_SLAVE    0
#define SPI_MASTER    1

#define UNIDIRECTION   0
#define BIDIRECTION    1

#define FIRST_SCLK_EDGE   0
#define SECOND_SCLK_EDGE  1

#define LOW_IDLE    0
#define HIGH_IDLE    1

#define CLOCK_NOT_ASSERT  0
#define CLOCK_ASSERT   1

#define TX_RX_NO_CONCURRENT  0
#define TX_RX_CONCURRENT  1

#define LENGTH_4BITS            0x03
#define LENGTH_5BITS            0x04
#define LENGTH_6BITS            0x05
#define LENGTH_7BITS            0x06
#define LENGTH_8BITS            0x07
#define LENGTH_9BITS            0x08
#define LENGTH_10BITS           0x09
#define LENGTH_11BITS           0x0a
#define LENGTH_12BITS           0x0b
#define LENGTH_13BITS           0x0c
#define LENGTH_14BITS           0x0d
#define LENGTH_15BITS           0x0e
#define LENGTH_16BITS           0x0f
#else

// Config SPI flow control register
#define UNIDIRECTION   (0<<1)        // Enable bidirection mode
#define BIDIRECTION    (1<<1)

#define MSB_FIRST               (0<<2)
#define LSB_FIRST               (1<<2)        // Enable LSB first mode

#define SCLK_1ST_EdGE           (0<<3)
#define SCLK_2ND_EdGE           (1<<3)

#define LOW_IDLE    (0<<4)        /* SCLK is low when idle */
#define HIGH_IDLE    (1<<4)        /* SCLK is high when idle */

#define TX_RX_NO_CONCURRENT  (0<<5)
#define TX_RX_CONCURRENT  (1<<5)        // Tx & Rx concurrent mode enable

#define CLOCK_NOT_ASSERT  (0<<8)
#define CLOCK_ASSERT   (1<<8)       // SPI clock idle enable control

#define LENGTH_4BITS            0x03<<10
#define LENGTH_5BITS            0x04<<10
#define LENGTH_6BITS            0x05<<10
#define LENGTH_7BITS            0x06<<10
#define LENGTH_8BITS            0x07<<10
#define LENGTH_9BITS            0x08<<10
#define LENGTH_10BITS           0x09<<10
#define LENGTH_11BITS           0x0a<<10
#define LENGTH_12BITS           0x0b<<10
#define LENGTH_13BITS           0x0c<<10
#define LENGTH_14BITS           0x0d<<10
#define LENGTH_15BITS           0x0e<<10
#define LENGTH_16BITS           0x0f<<10
#endif

//===================================================================

#define  SPI_REG_BASE   APB0_SPI_BASE

/*********************************************************************
 ENUMERATIONS AND STRUCTURES
*********************************************************************/

typedef volatile struct SPIReg
{
    REG32 SPI_TxR;     /* SPI master controller transmit FIFO input */
    REG32 SPI_IER;     /* Enable/Mask interrupts generated by the SPI master controller */
    REG32 SPI_FCR;     /* SPI master controller FIFO control register */
    REG32 SPI_FWCR;    /* SPI master controller transaction flow control register */
    REG32 SPI_DLYCR;   /* SPI master controller delay control register */
    REG32 SPI_TxCR;    /* Transmit counter */
    REG32 SPI_RxCR;    /* Receive counter */
    REG32 SPI_SSCR;    /* SPI master controller slave select and characteristic register */
    REG32 SPI_ISR;     /* SPI master controller interrupt status register */
} SPIReg_t, *pSPIReg_t;

#define SPI_RxR SPI_TxR  /* SPI master controller receiver FIFO input */

// the cBuffer structure
typedef struct struct_cBuffer
{
    unsigned char *dataptr;                 // the physical memory address where the buffer is stored
    unsigned short size;                    // the allocated size of the buffer
    unsigned short datalength;              // the length of the data currently in the buffer
    unsigned short dataindex;               // the index into the buffer where the data starts
} cBuffer;

/*********************************************************************
 FUNCTION PROTOTYPES
*********************************************************************/

BOOL SPI_PowerOnInit(void);
int SPI_Config(UINT32 spiconfig);
UINT16 SPI_Read(UINT8 *pdata, UINT16 size, UINT8 config);
UINT16 SPI_Write(UINT8 *pdata, UINT16 size, UINT8 config);
BOOL SPI_PowerOffDeinit(void);

#endif /* _SPI_H */

/*********************************************************************
 END OF FILE
*********************************************************************/