hw_memmap.h

瑞星微公司RK27XX系列芯片的SDK开发包

/******************************************************************/
/*   Copyright (C) 2007 ROCK-CHIPS FUZHOU . All Rights Reserved.  */
/*******************************************************************
File :  hw_memmap.h
Desc :  memory map address/device base address

Author : huangxinyu
Date : 2007-05-30
Notes :

$Log: hw_memmap.h,v $
Revision 1.5  2007/11/10 04:24:12  Huangxinyu
调试修改

Revision 1.4  2007/10/15 09:04:01  Huangxinyu
根据RK27提交修改driver

Revision 1.3  2007/10/08 02:38:41  Lingzhaojun
添加版本自动注释脚本

*********************************************************************/
#ifndef _HW_MEMMAP_H
#define _HW_MEMMAP_H

/********************************************************************
 GLOBAL MACROS DEFINE
********************************************************************/

// memory mapped address
#define AHB_SRAM                    0x00000000
#define BUS0IP_BASE                 0x18000000
#define BUS1IP_BASE                 0x18400000

#define FLASH_BANK0                 0x10000000
#define FLASH_BANK1                 0x11000000

#define MM_SDRAM_BANK0              0x60000000

#define ARM7CacheCtrl_BASE          0xEFFF0000
#define DSP_DMEM                    0x30000000
#define DSP_IMEM                    0x30040000
#define DSP_EPR                     0x30080000

// AHB0 device base address define
#define AHB0_EMD_SRAM               0x18200000
#define AHB0_ES6_BASE               0x18100000
#define AHB0_ES5_BASE               0x180FC000
#define AHB0_ES4_BASE               0x180F8000
#define AHB0_ES3_BASE               0x180F4000

#define AHB0_ROM_BASE               0x180EC000
#define AHB0_NANDC_BASE             0x180E8000
#define AHB0_VIP_BASE               0x180C0000
#define AHB0_SDRSTMC_BASE           0x180B0000
#define AHB0_UHC_BASE               0x180A4000
#define AHB0_UDC_BASE               0x180A0000
#define AHB0_A2A_DMA_BASE           0x18094000
#define AHB0_HDMA_BASE              0x18090000
#define AHB0_DEBUGIF_BASE           0x1808C000
#define AHB0_MAILBOX_BASE           0x18088000
#define AHB0_ARBITER_BASE           0x18084000
#define AHB0_INTC_BASE              0x18080000

// AHB1 device base address define
#define AHB1_DWDMA_BASE          0x186F0000
#define AHB1_HS_ADC_BASE      0x186EC000
#define AHB1_LCDC_BASE          0x186E8000
#define AHB1_ARBITER_BASE           0x18484000

// APB0 device base address define
#define APB0_GPIO2_BASE             0x18038000
#define APB0_ADC_BASE              0x18030000
#define APB0_PWM_BASE               0x1802C000
#define APB0_I2S_BASE               0x18028000
#define APB0_SD_BASE                0x18024000
#define APB0_I2C_BASE               0x18020000
#define APB0_SCU_BASE               0x1801C000
#define APB0_SPI_BASE               0x18018000
#define APB0_RTC_BASE               0x18014000
#define APB0_WDT_BASE               0x18010000
#define APB0_GPIO1_BASE             0x1800C000
#define APB0_UART1_BASE             0x18008000
#define APB0_UART0_BASE             0x18004000
#define APB0_TIMER_BASE             0x18000000

#define SDRAM_BASE          0x60000000

#endif /* _HW_MEMMAP_H */



/*********************************************************************
 END OF FILE
*********************************************************************/