📄 hw_dwdma.h
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/******************************************************************/
/* Copyright (C) 2007 ROCK-CHIPS FUZHOU . All Rights Reserved. */
/*******************************************************************
File : hw_Dwdma.h
Desc : Dwdma的寄存器定义
Author : nzy
Date :
Notes :
$Log :
*********************************************************************/
#ifndef _HW_DW_DMA_H_
#define _HW_DW_DMA_H_
#include "hw_memmap.h"
#define RegDWDMABase AHB1_DWDMA_BASE
#define DWDMA_SAR(chn) (RegDWDMABase+0x00+0x58*chn)
#define DWDMA_DAR(chn) (RegDWDMABase+0x08+0x58*chn)
#define DWDMA_LLP(chn) (RegDWDMABase+0x10+0x58*chn)
#define DWDMA_CTLL(chn) (RegDWDMABase+0x18+0x58*chn)
#define DWDMA_CTLH(chn) (RegDWDMABase+0x1c+0x58*chn)
#define DWDMA_SSTAT(chn) (RegDWDMABase+0x20+0x58*chn)
#define DWDMA_DSTAT(chn) (RegDWDMABase+0x28+0x58*chn)
#define DWDMA_SSTATAR(chn) (RegDWDMABase+0x30+0x58*chn)
#define DWDMA_DSTATAR(chn) (RegDWDMABase+0x38+0x58*chn)
#define DWDMA_CFGL(chn) (RegDWDMABase+0x40+0x58*chn)
#define DWDMA_CFGH(chn) (RegDWDMABase+0x44+0x58*chn)
#define DWDMA_SGR(chn) (RegDWDMABase+0x48+0x58*chn)
#define DWDMA_DSR(chn) (RegDWDMABase+0x50+0x58*chn)
#define DWDMA_RawTfr (RegDWDMABase+0x2c0)
#define DWDMA_RawBlock (RegDWDMABase+0x2c8)
#define DWDMA_RawSrcTran (RegDWDMABase+0x2d0)
#define DWDMA_RawDstTran (RegDWDMABase+0x2d8)
#define DWDMA_RawErr (RegDWDMABase+0x2e0)
#define DWDMA_StatusTfr (RegDWDMABase+0x2e8)
#define DWDMA_StatusBlock (RegDWDMABase+0x2f0)
#define DWDMA_StatusSrcTran (RegDWDMABase+0x2f8)
#define DWDMA_StatusDstTran (RegDWDMABase+0x300)
#define DWDMA_StatusErr (RegDWDMABase+0x308)
#define DWDMA_MaskTfr (RegDWDMABase+0x310)
#define DWDMA_MaskBlock (RegDWDMABase+0x318)
#define DWDMA_MaskSrcTran (RegDWDMABase+0x320)
#define DWDMA_MaskDstTran (RegDWDMABase+0x328)
#define DWDMA_MaskErr (RegDWDMABase+0x330)
#define DWDMA_ClearTfr (RegDWDMABase+0x338)
#define DWDMA_ClearBlock (RegDWDMABase+0x340)
#define DWDMA_ClearSrcTran (RegDWDMABase+0x348)
#define DWDMA_ClearDstTran (RegDWDMABase+0x350)
#define DWDMA_ClearErr (RegDWDMABase+0x358)
#define DWDMA_StatusInt (RegDWDMABase+0x360)
#define DWDMA_ReqSrcReg (RegDWDMABase+0x368)
#define DWDMA_ReqDstReg (RegDWDMABase+0x370)
#define DWDMA_SglReqSrcReg (RegDWDMABase+0x378)
#define DWDMA_SglReqDstReg (RegDWDMABase+0x380)
#define DWDMA_LstSrcReg (RegDWDMABase+0x388)
#define DWDMA_LstDstReg (RegDWDMABase+0x390)
#define DWDMA_DmaCfgReg (RegDWDMABase+0x398)
#define DWDMA_ChEnReg (RegDWDMABase+0x3a0)
#define DWDMA_DmaIdReg (RegDWDMABase+0x3a8)
#define DWDMA_DmaTestReg (RegDWDMABase+0x3b0)
//cfg low word
#define b_CFGL_CH_PRIOR(pri) (pri<<5)
#define b_CFGL_CH_SUSP (1<<8)
#define b_CFGL_FIFO_EMPTY (1<<9)
#define b_CFGL_H_SEL_DST (0<<10)
#define b_CFGL_S_SEL_DST (1<<10)
#define b_CFGL_H_SEL_SRC (0<<11)
#define b_CFGL_S_SEL_SRC (1<<11)
#define b_CFGL_LOCK_CH_L_OTF (0<<12)
#define b_CFGL_LOCK_CH_L_OBT (1<<12)
#define b_CFGL_LOCK_CH_L_OTN (2<<12)
#define b_CFGL_LOCK_B_L_OTF (0<<14)
#define b_CFGL_LOCK_B_L_OBT (1<<14)
#define b_CFGL_LOCK_B_L_OTN (2<<14)
#define b_CFGL_LOCK_CH_EN (0<<16)
#define b_CFGL_LOCK_B_EN (0<<17)
#define b_CFGL_DST_HS_POL_H (0<<18)
#define b_CFGL_DST_HS_POL_L (1<<18)
#define b_CFGL_SRC_HS_POL_H (0<<19)
#define b_CFGL_SRC_HS_POL_L (1<<19)
#define b_CFGL_RELOAD_SRC (1<<30)
#define b_CFGL_RELOAD_DST (1<<31)
//cfg high word
#define b_CFGH_FCMODE (1<<0)
#define b_CFGH_FIFO_MODE (1<<1)
#define b_CFGH_PROTCTL (1<<2)
#define b_CFGH_DS_UPD_EN (1<<5)
#define b_CFGH_SS_UPD_EN (1<<6)
#define b_CFGH_SRC_PER(HS) ((HS)<<7)
#define b_CFGH_DEST_PER(HS) ((HS)<<11)
//ctl low word
#define b_CTLL_INT_EN (1<<0)
#define b_CTLL_DST_TR_WIDTH_8 (0<<1)
#define b_CTLL_DST_TR_WIDTH_16 (1<<1)
#define b_CTLL_DST_TR_WIDTH_32 (2<<1)
#define b_CTLL_DST_TR_WIDTH_64 (3<<1)
#define b_CTLL_DST_TR_WIDTH_128 (4<<1)
#define b_CTLL_DST_TR_WIDTH_256 (5<<1)
#define b_CTLL_SRC_TR_WIDTH_8 (0<<4)
#define b_CTLL_SRC_TR_WIDTH_16 (1<<4)
#define b_CTLL_SRC_TR_WIDTH_32 (2<<4)
#define b_CTLL_SRC_TR_WIDTH_64 (3<<4)
#define b_CTLL_SRC_TR_WIDTH_128 (4<<4)
#define b_CTLL_SRC_TR_WIDTH_256 (5<<4)
#define b_CTLL_DINC_INC (0<<7)
#define b_CTLL_DINC_DEC (1<<7)
#define b_CTLL_DINC_UNC (2<<7)
#define b_CTLL_SINC_INC (0<<9)
#define b_CTLL_SINC_DEC (1<<9)
#define b_CTLL_SINC_UNC (2<<9)
#define b_CTLL_DEST_MSIZE_1 (0<<11)
#define b_CTLL_DEST_MSIZE_4 (1<<11)
#define b_CTLL_DEST_MSIZE_8 (2<<11)
#define b_CTLL_DEST_MSIZE_16 (3<<11)
#define b_CTLL_DEST_MSIZE_32 (4<<11)
#define b_CTLL_DEST_MSIZE_64 (5<<11)
#define b_CTLL_DEST_MSIZE_128 (6<<11)
#define b_CTLL_SRC_MSIZE_1 (0<<14)
#define b_CTLL_SRC_MSIZE_4 (1<<14)
#define b_CTLL_SRC_MSIZE_8 (2<<14)
#define b_CTLL_SRC_MSIZE_16 (3<<14)
#define b_CTLL_SRC_MSIZE_32 (4<<14)
#define b_CTLL_SRC_MSIZE_64 (5<<14)
#define b_CTLL_SRC_MSIZE_128 (6<<14)
#define b_CTLL_SRC_GATHER_EN (1<<17)
#define b_CTLL_DST_SCATTER_EN (1<<18)
#define b_CTLL_MEM2MEM_DWDMA (0<<20)
#define b_CTLL_MEM2PER_DWDMA (1<<20)
#define b_CTLL_PER2MEM_DWDMA (2<<20)
#define b_CTLL_PER2PER_DWDMA (3<<20)
#define b_CTLL_DMS_AM0 (0<<23)
#define b_CTLL_DMS_AM1 (1<<23)
#define b_CTLL_DMS_AM2 (2<<23)
#define b_CTLL_DMS_AM3 (3<<23)
#define b_CTLL_SMS_AM0 (0<<25)
#define b_CTLL_SMS_AM1 (1<<25)
#define b_CTLL_SMS_AM2 (2<<25)
#define b_CTLL_SMS_AM3 (3<<25)
#define b_CTLL_LLP_DST_EN (1<<27)
#define b_CTLL_LLP_SRC_EN (1<<28)
#define b_DWDMA_ENABLE 0x0001
#define b_DWDMA_DISABLE 0x0000
#define b_DWDMA_CHEN(chn) (0x00000101<<chn)
#define b_DWDMA_CLRISR 0xff
#define b_DWDMA_CLRCHN 0xf00
#define DWDMA_CHNTOLNUM 4
#define DWDMA_INITBLOCK 100
typedef enum
{
HS4 = 4,
HS5,
HS6,
HS7
}DWDMA_HSIF;
typedef enum
{
INC_INC = 0,
INC_UNC,
UNC_INC,
UNC_UNC
}DWDMA_ADDTYPE;
typedef enum
{
MEM2MEM = 0,
MEM2PER,
PER2MEM,
PER2PER
}DWDMA_HSTYPE;
#endif/* _HW_DWDMA_H_ */
/*********************************************************************
END OF FILE
*********************************************************************/
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