hw_timer.h

瑞星微公司RK27XX系列芯片的SDK开发包

/******************************************************************/
/*   Copyright (C) 2007 ROCK-CHIPS FUZHOU . All Rights Reserved.  */
/*******************************************************************
File :  timer.h
Desc :  定义Timer的寄存器结构体\寄存器位的宏定义\接口函数

Author : huangxinyu
Date : 2007-05-31
Notes :

$Log: hw_timer.h,v $
Revision 1.3  2007/10/08 02:38:50  Lingzhaojun
添加版本自动注释脚本

*********************************************************************/

#ifndef _TIMER_H
#define _TIMER_H

/********************************************************************
 INCLUDE FILES
*********************************************************************/
#include "hw_include.h"
/********************************************************************
 GLOBAL MACROS DEFINE
********************************************************************/

#define UserTimerNo           0   //   Timer 0
#define TIMER_REG_BASE  APB0_TIMER_BASE


// only for watchdog test -- begin
#define TMR_EN                (1<<8)
#define TMR_PERIOD_MODE       (1<<7)  // 0:free-running, 1:periodical
#define TMR_PRESCALE_SHIFT    4
#define TMR_IMASK             (1<<3)
#define TMR_INT_CLEAR         (1<<2)
#define TMR0_SET_FLAG(flag)   (SetRegBits32(PORSCHE_TMR0CON, flag))
#define TMR0_CLR_FLAG(flag)   (ClrRegBits32(PORSCHE_TMR0CON, flag))
#define TMR0_CLR_INT()    (ClrRegBits32(PORSCHE_TMR0CON, 0x04))
#define TMR0_INT_CLEAR()   TMR0_SET_FLAG(TMR_INT_CLEAR)
#define TMR0_EN()     TMR0_SET_FLAG(TMR_EN)
#define TMR0_DIS()     TMR0_CLR_FLAG(TMR_EN)
#define TMR0_PERIOD_MODE()   TMR0_SET_FLAG(TMR_PERIOD_MODE)
#define TMR0_FREE_RUN_MODE()  TMR0_CLR_FLAG(TMR_PERIOD_MODE)
#define TMR0_PRESCALE(x)   MaskRegBits32(PORSCHE_TMR0CON, ~0xffffff8f, (x) << TMR_PRESCALE_SHIFT)
// only for watchdog test -- end

/*
 *  Registers
 *  */
#define PORSCHE_TMR0LR 0x0000 /* load register */
#define PORSCHE_TMR0CVR 0x0004 /* current value register */
#define PORSCHE_TMR0CON 0x0008 /* control register */
#define PORSCHE_TMR1LR 0x0010 /* load register */
#define PORSCHE_TMR1CVR 0x0014 /* current value register */
#define PORSCHE_TMR1CON 0x0018 /* control register */
#define PORSCHE_TMR2LR 0x0020 /* load register */
#define PORSCHE_TMR2CVR 0x0024 /* current value register */
#define PORSCHE_TMR2CON 0x0028 /* control register */
#define PORSCHE_TMRMODE 0x0030 /* chain mode register */

/*
 *  PORSCHE_TMRxCON
 *  */
/* Timer enable/disable */
#define PORSCHE_TIMER_DIS 0x0 /* disable */
#define PORSCHE_TIMER_EN (0x1 << 8) /* enable*/

/* Timer counting mode selection */
#define PORSCHE_TIMER_CNT_MODE_FREE_RUNNING 0x0 /* free-running */
#define PORSCHE_TIMER_CNT_MODE_PERIODICAL (0x1 << 7) /* periodical */

/* Prescale factor */
#define PORSCHE_TIMER_PRESCALE_FACTOR_1_1 0x0 /* 1 */
#define PORSCHE_TIMER_PRESCALE_FACTOR_1_4 (0x1 << 4) /* 1/4 */
#define PORSCHE_TIMER_PRESCALE_FACTOR_1_8 (0x2 << 4) /* 1/8 */
#define PORSCHE_TIMER_PRESCALE_FACTOR_1_16 (0x3 << 4) /* 1/16 */
#define PORSCHE_TIMER_PRESCALE_FACTOR_1_32 (0x4 << 4) /* 1/32 */
#define PORSCHE_TIMER_PRESCALE_FACTOR_1_64 (0x5 << 4) /* 1/64 */
#define PORSCHE_TIMER_PRESCALE_FACTOR_1_128 (0x6 << 4) /* 1/128 */
#define PORSCHE_TIMER_PRESCALE_FACTOR_1_256 (0x7 << 4) /* 1/256 */

/* Interrupt mask */
#define PORSCHE_TIMER_INT_MASK_DIS 0x0 /* disable */
#define PORSCHE_TIMER_INT_MASK_EN (0x1 << 3) /* enable */

/* Interrupt clear */
#define PORSCHE_TIMER_INT_FLAG (0x1 << 2) /* this bit is set when an interrupt is pending
* writing a '0' to this bit will clear the interrupt*/

/* Interrupt control bit */
#define PORSCHE_TIMER_INT_EDGE_TRIG 0x0 /* edge-triggered */
#define PORSCHE_TIMER_INT_LEVEL_TRIG (0x1 << 1) /* level-triggered */

/*
 *  PORSCHE_TMRMODE
 *  */
#define PORSCHE_TIMER_CHAIN_MODE_0 0x0 /* mode 0: timer0 or timer1 or timer2 */
#define PORSCHE_TIMER_CHAIN_MODE_1 0x1 /* mode 1: chain timer0 and timer1 */
#define PORSCHE_TIMER_CHAIN_MODE_2 0x2 /* mode 2: chain timer0 and timer 1 and timer2 */

/*********************************************************************
 ENUMERATIONS AND STRUCTURES
*********************************************************************/
typedef enum
{
    PRESCALE_1,
    PRESCALE_4 ,
    PRESCALE_8 ,
    PRESCALE_16,
    PRESCALE_32,
    PRESCALE_64,
    PRESCALE_128,
    PRESCALE_256
}Timer_prescale_t;
typedef volatile struct TimerReg
{
    REG32 TMR0LR;   /* Timer 0 Load register */
    REG32 TMR0CVR;  /* Timer 0 Current value register */
    REG32 TMR0CON;  /* Timer 0 Control register */
    REG32 UNUSE0;
    REG32 TMR1LR;   /* Timer 1 Load register */
    REG32 TMR1CVR;  /* Timer 1 Current value register */
    REG32 TMR1CON;  /* Timer 1 Control register */
    REG32 UNUSE1;
    REG32 TMR2LR;   /* Timer 2 Load register */
    REG32 TMR2CVR;  /* Timer 2 Current value register */
    REG32 TMR2CON;  /* Timer 2 Control register */
} TimerReg_t, *pTimerReg_t;

/*********************************************************************
 FUNCTION PROTOTYPES
*********************************************************************/
#endif  /* _TIMER_H */

/*********************************************************************
 END OF FILE
*********************************************************************/