hw_scu.h

瑞星微公司RK27XX系列芯片的SDK开发包

/*********************************************************************************
*     Copyright (C),2004-2005,  Fuzhou Rockchip Co.,Ltd.
*         All Rights Reserved
*          V1.00
* FileName :  Hw_scu.h
* Author :  lzy
* Description:
* History  :
*   <author>  <time>    <version>    <desc>
*    lzy     07/6/29    1.0    ORG
*
$Log: Hw_scu.h,v $
Revision 1.4  2007/10/23 08:22:26  Huangxinyu
调试后修改bug

Revision 1.3  2007/10/15 09:03:25  Huangxinyu
根据RK27提交修改driver

Revision 1.2  2007/10/08 02:38:39  Lingzhaojun
添加版本自动注释脚本


*********************************************************************************/
#ifndef _HW_SCU_H
#define _HW_SCU_H

#define    OTP_CLK_DIS              (1<<0)
#define    DSP_CLK_DIS              (1<<1)
#define    SDRAM_CLK_DIS        (1<<2)
#define    HDMA_CLK_DIS         (1<<3)
#define    DWDMA_CLK_DIS      (1<<4)
#define    UHC_CLK_DIS              (1<<5)
#define    UDC_CLK_DIS              (1<<6)
#define    NAND_CLK_DIS              (1<<9)
#define    A2A_HCLK_DIS              (1<<10)
#define    SRAM_CLK_DIS              (1<<11)
#define    LCD_HCLK_DIS              (1<<12)
#define    LCD_CLK_DIS              (1<<13)
#define    VIP_HCLK_DIS              (1<<14)
#define    VIP_CLK_DIS              (1<<15)
#define    I2S_CLK_DIS              (1<<16)
#define    I2S_PCLK_DIS              (1<<17)
#define    UART0_CLK_DIS              (1<<18)
#define    UART1_CLK_DIS              (1<<19)
#define    I2C_CLK_DIS              (1<<20)
#define    SPI_CLK_DIS              (1<<21)
#define    SDMMC_CLK_DIS              (1<<22)
#define    LSADC_CLK_DIS              (1<<23)
#define    LSADC_PCLK_DIS              (1<<24)
#define    HSADC_CLK_DIS              (1<<25)
#define    HSADC_HCLK_DIS              (1<<26)
#define    GPIO_CLK_DIS              (1<<27)
#define    TIMER_CLK_DIS              (1<<28)
#define    PWM_CLK_DIS              (1<<29)
#define    RTC_CLK_DIS              (1<<30)
#define    WDT_CLK_DIS              (1<<31)


typedef volatile struct SCUReg
{
    REG32 SCU_IDREG;
    REG32 SCU_REMAP;
    REG32 SCU_PLLARM;
    REG32 SCU_PLLDSP;
    REG32 SCU_PLLAUX;
    REG32 SCU_DIVCON;
    REG32 SCU_CLKCFG;
    REG32 SCU_RSTCFG;
    REG32 SCU_PWM;
    REG32 SCU_CPUPD;
    REG32 SCU_CHIPCFG;
    REG32 SCU_STATUS;
}SCUReg_t, *pSCUReg_t;

#define  pSCUReg  ((pSCUReg_t)APB0_SCU_BASE)        //0x1801C000


//SCU_ID
#define SCU_ID    0xA1000604

//SCU_REMAP
#define REMAP_ID   0xdeadbeef

//SCU_PLLARM, SCU_PLLDSP, SCU_PLLAUX
#define PLL_SBE    (0x01<<24)
#define PLL_EN    (0x01<<23)
#define PLL_PD    (0x01<<22)

#define CLKR_SHIFT   (16)
#define CLKR_MASK   (0x3f<<CLKR_SHIFT)
#define CLKF_SHIFT   (4)
#define CLKF_MASK   (0xfff<<CLKF_SHIFT)
#define CLKOD_SHIFT   (1)
#define CLKOD_MASK   (0x7<<CLKF_SHIFT)

#define PLL_BYPASS   0x01

//SCU_DIVCON
#define PHY_CLK12M   (0x01<<31)
#define SENSOR_CLK24  (0x00<<29)
#define SENSOR_CLK48  (0x01<<29)
#define SENSOR_CLK27  (0x02<<29)

#define LCDC_CLKEXT   (0x01<<28)
#define LCDC_CLKDIV_SHL  20;
#define LCDC_CLK_ARM  (0x00<<18)
#define LCDC_CLK_DSP  (0x01<<18)
#define LCDC_CLK_AUX  (0x02<<18)


#define ADC_CLKDIV_SHL  10
#define ADC_CLKDIV_MASK (0xff<<ADC_CLKDIV_SHL)

#define CODEC_CLK12M   (0x01<<9)
#define CODEC_CLKDIV_SHL  5

// PCLK
#define PCLK_MASK   (3<<3)
#define PCLK_SHIHL   (3)

//HCLK div
#define HCLK_MASK   (1<<2)
#define HCLK_SHIHL    (2)


#define DSP_SLOW_MASK  (0x01<<1)
#define DSP_SLOW    (0x01<<1)
#define DSP_NORMAL    (0x00<<1)
#define ARM_SLOW_MASK  (0x01<<0)
#define ARM_NORMAL   (0x00<<0)
#define ARM_SLOW   (0x01<<0)

//SCU_CPUPD
#define ARMPD_ID   0xdeadbabe


#endif      //_HW_SCU_H//