post.c

北京瑞泰的bootloader例程

#define PLL_BASE_ADDR   0x01b7c000
#define PLL_PID         ( PLL_BASE_ADDR + 0x000 )
#define PLL_CSR         ( PLL_BASE_ADDR + 0x100 )
#define PLL_MULT        ( PLL_BASE_ADDR + 0x110 )
#define PLL_DIV0        ( PLL_BASE_ADDR + 0x114 )
#define PLL_DIV1        ( PLL_BASE_ADDR + 0x118 )
#define PLL_DIV2        ( PLL_BASE_ADDR + 0x11C )
#define PLL_DIV3        ( PLL_BASE_ADDR + 0x120 )
#define PLL_OSCDIV1     ( PLL_BASE_ADDR + 0x124 )
#define CSR_PLLEN          0x00000001
#define CSR_PLLPWRDN       0x00000002
#define CSR_PLLRST         0x00000008 
#define CSR_PLLSTABLE      0x00000040
#define DIV_ENABLE         0x00008000
#define EMIF_GCTL       0x01800000
#define EMIF_CE1        0x01800004
#define EMIF_CE0        0x01800008
#define EMIF_CE2        0x01800010
#define EMIF_CE3        0x01800014
#define EMIF_SDRAMCTL   0x01800018
#define EMIF_SDRAMTIM   0x0180001C
#define EMIF_SDRAMEXT   0x01800020
#define EMIF_CCFG       0x01840000;
#define SDRAM_BASE_ADDRESS    0x80000000
#define SDRAM_SIZE      0x400000
#define EIP  *(int *)0x19c0008
#define IML  *(int *)0x19c0004
#define IMH  *(int *)0x19c0000
#define TIM0_CTL  *(int *)0x1940000
#define TIM0_PRD  *(int *)0x1940004
#define TIM0_CNT  *(int *)0x1940008
#define LED       *(char *)0x90100000
cregister unsigned int IER,CSR,IFR,ICR,ISTP;
void init_emif( void );
void  init_pll( void );
void interrupt time( void );
void initInterrupt(void);
void initTime0( void );
main()
{
    init_pll();
    init_emif();
    initInterrupt();
    initTime0();
    LED =0x5;
    for(;;);
}
void interrupt time( void )
{
     char i;
     i= LED;
     LED =~i;
}
void initInterrupt(void)
{
	CSR=CSR&0xfffffffe;
	ISTP=0x800;
   	EIP=0x0;
   	IMH=0;
   	IML=0x18a1;
   	ICR=0xff;	
	IER=0x13;
	CSR=CSR|1; 	
}
void initTime0( void )
{
  TIM0_CTL =0x200;
  TIM0_PRD = 0xffffff;
  TIM0_CNT= 0;
  TIM0_CTL =0x2c0;
}

void init_emif( void )
{
	*(int *)EMIF_GCTL     = 0x00000078;
	*(int *)EMIF_CE0      = 0xffffff93;  /* CE0 SDRAM                     */
	*(int *)EMIF_CE1      = 0xffffff13;  /* CE1 Flash 16-bit               */
	*(int *)EMIF_SDRAMCTL = 0x53115000;  /* SDRAM control                 */
	*(int *)EMIF_SDRAMTIM = 0x00000578;  /* SDRAM timing (refresh)        */
	*(int *)EMIF_SDRAMEXT = 0x000a8529;  /* SDRAM Extension register      */
}

void  init_pll( void )
{
    *(int *)PLL_CSR  &= ~CSR_PLLEN;
    *(int *)PLL_CSR  |= CSR_PLLRST;
    *(int *)PLL_DIV0    = DIV_ENABLE + 0;  
    *(int *)PLL_MULT    = 8;               
    *(int *)PLL_OSCDIV1 = DIV_ENABLE + 4;
    *(int *)PLL_DIV3    = DIV_ENABLE + 3; 
    *(int *)PLL_DIV2    = DIV_ENABLE + 3; 
    *(int *)PLL_DIV1    = DIV_ENABLE + 1; 
    *(int *)PLL_CSR  &= ~CSR_PLLRST;
    *(int *)PLL_CSR |= CSR_PLLEN;

}