usrp_radar_mono.qsf

这是用python语言写的一个数字广播的信号处理工具包。利用它

set_location_assignment PIN_54 -to tx_b[13]
set_location_assignment PIN_158 -to TXSYNC_A
set_location_assignment PIN_37 -to TXSYNC_B
set_location_assignment PIN_235 -to io_rx_b[15]
set_location_assignment PIN_24 -to io_tx_b[15]
set_location_assignment PIN_213 -to io_rx_a[15]
set_location_assignment PIN_194 -to io_tx_a[15]
set_location_assignment PIN_1 -to MYSTERY_SIGNAL

# Classic Timing Assignments
# ==========================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
set_global_assignment -name MAX_SCC_SIZE 50

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name USER_LIBRARIES "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
set_global_assignment -name TOP_LEVEL_ENTITY usrp_radar_mono

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name INC_PLC_MODE OFF
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"

# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME "0 ns"
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE

# Design Assistant Assignments
# ============================
set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
set_global_assignment -name ASSG_CAT OFF
set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
set_global_assignment -name CLK_CAT OFF
set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
set_global_assignment -name CLK_RULE_INV_CLOCK OFF
set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
set_global_assignment -name CLK_RULE_MIX_EDGES OFF
set_global_assignment -name RESET_CAT OFF
set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name TIMING_CAT OFF
set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
set_global_assignment -name SIGNALRACE_CAT OFF
set_global_assignment -name ACLK_CAT OFF
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
set_global_assignment -name HCPY_CAT OFF
set_global_assignment -name HCPY_VREF_PINS OFF
set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, D101, D102, D103, H102"
set_global_assignment -name DISABLE_DA_RULE H101

# SignalTap II Assignments
# ========================
set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
set_global_assignment -name ENABLE_SIGNALTAP OFF

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

# start CLOCK(SCLK)
# -----------------

	# Classic Timing Assignments
	# ==========================
set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK

# end CLOCK(SCLK)
# ---------------

# start CLOCK(master_clk)
# -----------------------

	# Classic Timing Assignments
	# ==========================
set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk

# end CLOCK(master_clk)
# ---------------------

# start CLOCK(usbclk)
# -------------------

	# Classic Timing Assignments
	# ==========================
set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk

# end CLOCK(usbclk)
# -----------------

# -----------------------------
# start ENTITY(usrp_radar_mono)

	# Classic Timing Assignments
	# ==========================
set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk

	# start DESIGN_PARTITION(Top)
	# ---------------------------

		# Incremental Compilation Assignments
		# ===================================
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

	# end DESIGN_PARTITION(Top)
	# -------------------------

# end ENTITY(usrp_radar_mono)
# ---------------------------
set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
set_global_assignment -name VERILOG_FILE dacpll.v
set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
set_global_assignment -name VERILOG_FILE ../lib/fifo32_2k.v
set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
set_global_assignment -name VERILOG_FILE ../lib/radar.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v