accum32.v

这是用python语言写的一个数字广播的信号处理工具包。利用它

// megafunction wizard: %ALTACCUMULATE%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altaccumulate 

// ============================================================
// File Name: accum32.v
// Megafunction Name(s):
// 			altaccumulate
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************


//Copyright (C) 1991-2003 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
//any other  silicon devices,  unless such use is  explicitly  licensed under
//a separate agreement with  Altera  or a megafunction partner.  Title to the
//intellectual property,  including patents,  copyrights,  trademarks,  trade
//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
//support  information,  device programming or simulation file,  or any other
//related documentation or information provided by  Altera  or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.


//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END

//synthesis_resources = lut 32 
module  accum32_accum_nta
	( 
	aclr,
	clken,
	clock,
	data,
	result) /* synthesis synthesis_clearbox=1 */;
	input   aclr;
	input   clken;
	input   clock;
	input   [31:0]  data;
	output   [31:0]  result;

	wire  [0:0]   wire_acc_cella_0cout;
	wire  [0:0]   wire_acc_cella_1cout;
	wire  [0:0]   wire_acc_cella_2cout;
	wire  [0:0]   wire_acc_cella_3cout;
	wire  [0:0]   wire_acc_cella_4cout;
	wire  [0:0]   wire_acc_cella_5cout;
	wire  [0:0]   wire_acc_cella_6cout;
	wire  [0:0]   wire_acc_cella_7cout;
	wire  [0:0]   wire_acc_cella_8cout;
	wire  [0:0]   wire_acc_cella_9cout;
	wire  [0:0]   wire_acc_cella_10cout;
	wire  [0:0]   wire_acc_cella_11cout;
	wire  [0:0]   wire_acc_cella_12cout;
	wire  [0:0]   wire_acc_cella_13cout;
	wire  [0:0]   wire_acc_cella_14cout;
	wire  [0:0]   wire_acc_cella_15cout;
	wire  [0:0]   wire_acc_cella_16cout;
	wire  [0:0]   wire_acc_cella_17cout;
	wire  [0:0]   wire_acc_cella_18cout;
	wire  [0:0]   wire_acc_cella_19cout;
	wire  [0:0]   wire_acc_cella_20cout;
	wire  [0:0]   wire_acc_cella_21cout;
	wire  [0:0]   wire_acc_cella_22cout;
	wire  [0:0]   wire_acc_cella_23cout;
	wire  [0:0]   wire_acc_cella_24cout;
	wire  [0:0]   wire_acc_cella_25cout;
	wire  [0:0]   wire_acc_cella_26cout;
	wire  [0:0]   wire_acc_cella_27cout;
	wire  [0:0]   wire_acc_cella_28cout;
	wire  [0:0]   wire_acc_cella_29cout;
	wire  [0:0]   wire_acc_cella_30cout;
	wire  [31:0]   wire_acc_cella_dataa;
	wire  [31:0]   wire_acc_cella_datab;
	wire  [31:0]   wire_acc_cella_datac;
	wire  [31:0]   wire_acc_cella_regout;
	wire sload;

	stratix_lcell   acc_cella_0
	( 
	.aclr(aclr),
	.cin(1'b0),
	.clk(clock),
	.cout(wire_acc_cella_0cout[0:0]),
	.dataa(wire_acc_cella_dataa[0:0]),
	.datab(wire_acc_cella_datab[0:0]),
	.datac(wire_acc_cella_datac[0:0]),
	.ena(clken),
	.regout(wire_acc_cella_regout[0:0]),
	.sload(sload));
	defparam
		acc_cella_0.cin_used = "true",
		acc_cella_0.lut_mask = "96e8",
		acc_cella_0.operation_mode = "arithmetic",
		acc_cella_0.sum_lutc_input = "cin",
		acc_cella_0.synch_mode = "on",
		acc_cella_0.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_1
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_0cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_1cout[0:0]),
	.dataa(wire_acc_cella_dataa[1:1]),
	.datab(wire_acc_cella_datab[1:1]),
	.datac(wire_acc_cella_datac[1:1]),
	.ena(clken),
	.regout(wire_acc_cella_regout[1:1]),
	.sload(sload));
	defparam
		acc_cella_1.cin_used = "true",
		acc_cella_1.lut_mask = "96e8",
		acc_cella_1.operation_mode = "arithmetic",
		acc_cella_1.sum_lutc_input = "cin",
		acc_cella_1.synch_mode = "on",
		acc_cella_1.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_2
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_1cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_2cout[0:0]),
	.dataa(wire_acc_cella_dataa[2:2]),
	.datab(wire_acc_cella_datab[2:2]),
	.datac(wire_acc_cella_datac[2:2]),
	.ena(clken),
	.regout(wire_acc_cella_regout[2:2]),
	.sload(sload));
	defparam
		acc_cella_2.cin_used = "true",
		acc_cella_2.lut_mask = "96e8",
		acc_cella_2.operation_mode = "arithmetic",
		acc_cella_2.sum_lutc_input = "cin",
		acc_cella_2.synch_mode = "on",
		acc_cella_2.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_3
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_2cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_3cout[0:0]),
	.dataa(wire_acc_cella_dataa[3:3]),
	.datab(wire_acc_cella_datab[3:3]),
	.datac(wire_acc_cella_datac[3:3]),
	.ena(clken),
	.regout(wire_acc_cella_regout[3:3]),
	.sload(sload));
	defparam
		acc_cella_3.cin_used = "true",
		acc_cella_3.lut_mask = "96e8",
		acc_cella_3.operation_mode = "arithmetic",
		acc_cella_3.sum_lutc_input = "cin",
		acc_cella_3.synch_mode = "on",
		acc_cella_3.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_4
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_3cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_4cout[0:0]),
	.dataa(wire_acc_cella_dataa[4:4]),
	.datab(wire_acc_cella_datab[4:4]),
	.datac(wire_acc_cella_datac[4:4]),
	.ena(clken),
	.regout(wire_acc_cella_regout[4:4]),
	.sload(sload));
	defparam
		acc_cella_4.cin_used = "true",
		acc_cella_4.lut_mask = "96e8",
		acc_cella_4.operation_mode = "arithmetic",
		acc_cella_4.sum_lutc_input = "cin",
		acc_cella_4.synch_mode = "on",
		acc_cella_4.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_5
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_4cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_5cout[0:0]),
	.dataa(wire_acc_cella_dataa[5:5]),
	.datab(wire_acc_cella_datab[5:5]),
	.datac(wire_acc_cella_datac[5:5]),
	.ena(clken),
	.regout(wire_acc_cella_regout[5:5]),
	.sload(sload));
	defparam
		acc_cella_5.cin_used = "true",
		acc_cella_5.lut_mask = "96e8",
		acc_cella_5.operation_mode = "arithmetic",
		acc_cella_5.sum_lutc_input = "cin",
		acc_cella_5.synch_mode = "on",
		acc_cella_5.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_6
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_5cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_6cout[0:0]),
	.dataa(wire_acc_cella_dataa[6:6]),
	.datab(wire_acc_cella_datab[6:6]),
	.datac(wire_acc_cella_datac[6:6]),
	.ena(clken),
	.regout(wire_acc_cella_regout[6:6]),
	.sload(sload));
	defparam
		acc_cella_6.cin_used = "true",
		acc_cella_6.lut_mask = "96e8",
		acc_cella_6.operation_mode = "arithmetic",
		acc_cella_6.sum_lutc_input = "cin",
		acc_cella_6.synch_mode = "on",
		acc_cella_6.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_7
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_6cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_7cout[0:0]),
	.dataa(wire_acc_cella_dataa[7:7]),
	.datab(wire_acc_cella_datab[7:7]),
	.datac(wire_acc_cella_datac[7:7]),
	.ena(clken),
	.regout(wire_acc_cella_regout[7:7]),
	.sload(sload));
	defparam
		acc_cella_7.cin_used = "true",
		acc_cella_7.lut_mask = "96e8",
		acc_cella_7.operation_mode = "arithmetic",
		acc_cella_7.sum_lutc_input = "cin",
		acc_cella_7.synch_mode = "on",
		acc_cella_7.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_8
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_7cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_8cout[0:0]),
	.dataa(wire_acc_cella_dataa[8:8]),
	.datab(wire_acc_cella_datab[8:8]),
	.datac(wire_acc_cella_datac[8:8]),
	.ena(clken),
	.regout(wire_acc_cella_regout[8:8]),
	.sload(sload));
	defparam
		acc_cella_8.cin_used = "true",
		acc_cella_8.lut_mask = "96e8",
		acc_cella_8.operation_mode = "arithmetic",
		acc_cella_8.sum_lutc_input = "cin",
		acc_cella_8.synch_mode = "on",
		acc_cella_8.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_9
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_8cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_9cout[0:0]),
	.dataa(wire_acc_cella_dataa[9:9]),
	.datab(wire_acc_cella_datab[9:9]),
	.datac(wire_acc_cella_datac[9:9]),
	.ena(clken),
	.regout(wire_acc_cella_regout[9:9]),
	.sload(sload));
	defparam
		acc_cella_9.cin_used = "true",
		acc_cella_9.lut_mask = "96e8",
		acc_cella_9.operation_mode = "arithmetic",
		acc_cella_9.sum_lutc_input = "cin",
		acc_cella_9.synch_mode = "on",
		acc_cella_9.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_10
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_9cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_10cout[0:0]),
	.dataa(wire_acc_cella_dataa[10:10]),
	.datab(wire_acc_cella_datab[10:10]),
	.datac(wire_acc_cella_datac[10:10]),
	.ena(clken),
	.regout(wire_acc_cella_regout[10:10]),
	.sload(sload));
	defparam
		acc_cella_10.cin_used = "true",
		acc_cella_10.lut_mask = "96e8",
		acc_cella_10.operation_mode = "arithmetic",
		acc_cella_10.sum_lutc_input = "cin",
		acc_cella_10.synch_mode = "on",
		acc_cella_10.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_11
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_10cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_11cout[0:0]),
	.dataa(wire_acc_cella_dataa[11:11]),
	.datab(wire_acc_cella_datab[11:11]),
	.datac(wire_acc_cella_datac[11:11]),
	.ena(clken),
	.regout(wire_acc_cella_regout[11:11]),
	.sload(sload));
	defparam
		acc_cella_11.cin_used = "true",
		acc_cella_11.lut_mask = "96e8",
		acc_cella_11.operation_mode = "arithmetic",
		acc_cella_11.sum_lutc_input = "cin",
		acc_cella_11.synch_mode = "on",
		acc_cella_11.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_12
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_11cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_12cout[0:0]),
	.dataa(wire_acc_cella_dataa[12:12]),
	.datab(wire_acc_cella_datab[12:12]),
	.datac(wire_acc_cella_datac[12:12]),
	.ena(clken),
	.regout(wire_acc_cella_regout[12:12]),
	.sload(sload));
	defparam
		acc_cella_12.cin_used = "true",
		acc_cella_12.lut_mask = "96e8",
		acc_cella_12.operation_mode = "arithmetic",
		acc_cella_12.sum_lutc_input = "cin",
		acc_cella_12.synch_mode = "on",
		acc_cella_12.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_13
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_12cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_13cout[0:0]),
	.dataa(wire_acc_cella_dataa[13:13]),
	.datab(wire_acc_cella_datab[13:13]),
	.datac(wire_acc_cella_datac[13:13]),
	.ena(clken),
	.regout(wire_acc_cella_regout[13:13]),
	.sload(sload));
	defparam
		acc_cella_13.cin_used = "true",
		acc_cella_13.lut_mask = "96e8",
		acc_cella_13.operation_mode = "arithmetic",
		acc_cella_13.sum_lutc_input = "cin",
		acc_cella_13.synch_mode = "on",
		acc_cella_13.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_14
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_13cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_14cout[0:0]),
	.dataa(wire_acc_cella_dataa[14:14]),
	.datab(wire_acc_cella_datab[14:14]),
	.datac(wire_acc_cella_datac[14:14]),
	.ena(clken),
	.regout(wire_acc_cella_regout[14:14]),
	.sload(sload));
	defparam
		acc_cella_14.cin_used = "true",
		acc_cella_14.lut_mask = "96e8",
		acc_cella_14.operation_mode = "arithmetic",
		acc_cella_14.sum_lutc_input = "cin",
		acc_cella_14.synch_mode = "on",
		acc_cella_14.lpm_type = "stratix_lcell";
	stratix_lcell   acc_cella_15
	( 
	.aclr(aclr),
	.cin(wire_acc_cella_14cout[0:0]),
	.clk(clock),
	.cout(wire_acc_cella_15cout[0:0]),
	.dataa(wire_acc_cella_dataa[15:15]),
	.datab(wire_acc_cella_datab[15:15]),