fifo_4k.v

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// megafunction wizard: %FIFO%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo 

// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// 			dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************


//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic       
//functions, and any output files any of the foregoing           
//(including device programming or simulation files), and any    
//associated documentation or information are expressly subject  
//to the terms and conditions of the Altera Program License      
//Subscription Agreement, Altera MegaCore Function License       
//Agreement, or other applicable license agreement, including,   
//without limitation, that your use is for the sole purpose of   
//programming logic devices manufactured by Altera and sold by   
//Altera or its authorized distributors.  Please refer to the    
//applicable agreement for further details.


//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END

//synthesis_resources = 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  fifo_4k_a_gray2bin_9m4
	( 
	bin,
	gray) /* synthesis synthesis_clearbox=1 */;
	output   [11:0]  bin;
	input   [11:0]  gray;

	wire  xor0;
	wire  xor1;
	wire  xor10;
	wire  xor2;
	wire  xor3;
	wire  xor4;
	wire  xor5;
	wire  xor6;
	wire  xor7;
	wire  xor8;
	wire  xor9;

	assign
		bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
		xor0 = (gray[0] ^ xor1),
		xor1 = (gray[1] ^ xor2),
		xor10 = (gray[11] ^ gray[10]),
		xor2 = (gray[2] ^ xor3),
		xor3 = (gray[3] ^ xor4),
		xor4 = (gray[4] ^ xor5),
		xor5 = (gray[5] ^ xor6),
		xor6 = (gray[6] ^ xor7),
		xor7 = (gray[7] ^ xor8),
		xor8 = (gray[8] ^ xor9),
		xor9 = (gray[9] ^ xor10);
endmodule //fifo_4k_a_gray2bin_9m4


//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END

//synthesis_resources = lut 13 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  fifo_4k_a_graycounter_826
	( 
	aclr,
	clock,
	cnt_en,
	q) /* synthesis synthesis_clearbox=1 */;
	input   aclr;
	input   clock;
	input   cnt_en;
	output   [11:0]  q;

	wire  [0:0]   wire_countera_0cout;
	wire  [0:0]   wire_countera_1cout;
	wire  [0:0]   wire_countera_2cout;
	wire  [0:0]   wire_countera_3cout;
	wire  [0:0]   wire_countera_4cout;
	wire  [0:0]   wire_countera_5cout;
	wire  [0:0]   wire_countera_6cout;
	wire  [0:0]   wire_countera_7cout;
	wire  [0:0]   wire_countera_8cout;
	wire  [0:0]   wire_countera_9cout;
	wire  [0:0]   wire_countera_10cout;
	wire  [11:0]   wire_countera_regout;
	wire  wire_parity_cout;
	wire  wire_parity_regout;
	wire  [11:0]  power_modified_counter_values;
	wire sclr;
	wire updown;

	cyclone_lcell   countera_0
	( 
	.aclr(aclr),
	.cin(wire_parity_cout),
	.clk(clock),
	.combout(),
	.cout(wire_countera_0cout[0:0]),
	.dataa(cnt_en),
	.datab(wire_countera_regout[0:0]),
	.ena(1'b1),
	.regout(wire_countera_regout[0:0]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_0.cin_used = "true",
		countera_0.lut_mask = "c6a0",
		countera_0.operation_mode = "arithmetic",
		countera_0.sum_lutc_input = "cin",
		countera_0.synch_mode = "on",
		countera_0.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_1
	( 
	.aclr(aclr),
	.cin(wire_countera_0cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_1cout[0:0]),
	.dataa(power_modified_counter_values[0]),
	.datab(power_modified_counter_values[1]),
	.ena(1'b1),
	.regout(wire_countera_regout[1:1]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_1.cin_used = "true",
		countera_1.lut_mask = "6c50",
		countera_1.operation_mode = "arithmetic",
		countera_1.sum_lutc_input = "cin",
		countera_1.synch_mode = "on",
		countera_1.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_2
	( 
	.aclr(aclr),
	.cin(wire_countera_1cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_2cout[0:0]),
	.dataa(power_modified_counter_values[1]),
	.datab(power_modified_counter_values[2]),
	.ena(1'b1),
	.regout(wire_countera_regout[2:2]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_2.cin_used = "true",
		countera_2.lut_mask = "6c50",
		countera_2.operation_mode = "arithmetic",
		countera_2.sum_lutc_input = "cin",
		countera_2.synch_mode = "on",
		countera_2.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_3
	( 
	.aclr(aclr),
	.cin(wire_countera_2cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_3cout[0:0]),
	.dataa(power_modified_counter_values[2]),
	.datab(power_modified_counter_values[3]),
	.ena(1'b1),
	.regout(wire_countera_regout[3:3]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_3.cin_used = "true",
		countera_3.lut_mask = "6c50",
		countera_3.operation_mode = "arithmetic",
		countera_3.sum_lutc_input = "cin",
		countera_3.synch_mode = "on",
		countera_3.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_4
	( 
	.aclr(aclr),
	.cin(wire_countera_3cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_4cout[0:0]),
	.dataa(power_modified_counter_values[3]),
	.datab(power_modified_counter_values[4]),
	.ena(1'b1),
	.regout(wire_countera_regout[4:4]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_4.cin_used = "true",
		countera_4.lut_mask = "6c50",
		countera_4.operation_mode = "arithmetic",
		countera_4.sum_lutc_input = "cin",
		countera_4.synch_mode = "on",
		countera_4.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_5
	( 
	.aclr(aclr),
	.cin(wire_countera_4cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_5cout[0:0]),
	.dataa(power_modified_counter_values[4]),
	.datab(power_modified_counter_values[5]),
	.ena(1'b1),
	.regout(wire_countera_regout[5:5]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_5.cin_used = "true",
		countera_5.lut_mask = "6c50",
		countera_5.operation_mode = "arithmetic",
		countera_5.sum_lutc_input = "cin",
		countera_5.synch_mode = "on",
		countera_5.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_6
	( 
	.aclr(aclr),
	.cin(wire_countera_5cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_6cout[0:0]),
	.dataa(power_modified_counter_values[5]),
	.datab(power_modified_counter_values[6]),
	.ena(1'b1),
	.regout(wire_countera_regout[6:6]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_6.cin_used = "true",
		countera_6.lut_mask = "6c50",
		countera_6.operation_mode = "arithmetic",
		countera_6.sum_lutc_input = "cin",
		countera_6.synch_mode = "on",
		countera_6.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_7
	( 
	.aclr(aclr),
	.cin(wire_countera_6cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_7cout[0:0]),
	.dataa(power_modified_counter_values[6]),
	.datab(power_modified_counter_values[7]),
	.ena(1'b1),
	.regout(wire_countera_regout[7:7]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_7.cin_used = "true",
		countera_7.lut_mask = "6c50",
		countera_7.operation_mode = "arithmetic",
		countera_7.sum_lutc_input = "cin",
		countera_7.synch_mode = "on",
		countera_7.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_8
	( 
	.aclr(aclr),
	.cin(wire_countera_7cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_8cout[0:0]),
	.dataa(power_modified_counter_values[7]),
	.datab(power_modified_counter_values[8]),
	.ena(1'b1),
	.regout(wire_countera_regout[8:8]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)