fifo_2k.v

这是用python语言写的一个数字广播的信号处理工具包。利用它

	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_11.connectivity_checking = "OFF",
		ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_11.operation_mode = "dual_port",
		ram_block3a_11.port_a_address_width = 11,
		ram_block3a_11.port_a_data_width = 1,
		ram_block3a_11.port_a_first_address = 0,
		ram_block3a_11.port_a_first_bit_number = 11,
		ram_block3a_11.port_a_last_address = 2047,
		ram_block3a_11.port_a_logical_ram_depth = 2048,
		ram_block3a_11.port_a_logical_ram_width = 16,
		ram_block3a_11.port_b_address_clear = "none",
		ram_block3a_11.port_b_address_clock = "clock1",
		ram_block3a_11.port_b_address_width = 11,
		ram_block3a_11.port_b_data_out_clear = "none",
		ram_block3a_11.port_b_data_out_clock = "none",
		ram_block3a_11.port_b_data_width = 1,
		ram_block3a_11.port_b_first_address = 0,
		ram_block3a_11.port_b_first_bit_number = 11,
		ram_block3a_11.port_b_last_address = 2047,
		ram_block3a_11.port_b_logical_ram_depth = 2048,
		ram_block3a_11.port_b_logical_ram_width = 16,
		ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_11.ram_block_type = "auto",
		ram_block3a_11.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_12
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[12]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_12.connectivity_checking = "OFF",
		ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_12.operation_mode = "dual_port",
		ram_block3a_12.port_a_address_width = 11,
		ram_block3a_12.port_a_data_width = 1,
		ram_block3a_12.port_a_first_address = 0,
		ram_block3a_12.port_a_first_bit_number = 12,
		ram_block3a_12.port_a_last_address = 2047,
		ram_block3a_12.port_a_logical_ram_depth = 2048,
		ram_block3a_12.port_a_logical_ram_width = 16,
		ram_block3a_12.port_b_address_clear = "none",
		ram_block3a_12.port_b_address_clock = "clock1",
		ram_block3a_12.port_b_address_width = 11,
		ram_block3a_12.port_b_data_out_clear = "none",
		ram_block3a_12.port_b_data_out_clock = "none",
		ram_block3a_12.port_b_data_width = 1,
		ram_block3a_12.port_b_first_address = 0,
		ram_block3a_12.port_b_first_bit_number = 12,
		ram_block3a_12.port_b_last_address = 2047,
		ram_block3a_12.port_b_logical_ram_depth = 2048,
		ram_block3a_12.port_b_logical_ram_width = 16,
		ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_12.ram_block_type = "auto",
		ram_block3a_12.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_13
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[13]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_13.connectivity_checking = "OFF",
		ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_13.operation_mode = "dual_port",
		ram_block3a_13.port_a_address_width = 11,
		ram_block3a_13.port_a_data_width = 1,
		ram_block3a_13.port_a_first_address = 0,
		ram_block3a_13.port_a_first_bit_number = 13,
		ram_block3a_13.port_a_last_address = 2047,
		ram_block3a_13.port_a_logical_ram_depth = 2048,
		ram_block3a_13.port_a_logical_ram_width = 16,
		ram_block3a_13.port_b_address_clear = "none",
		ram_block3a_13.port_b_address_clock = "clock1",
		ram_block3a_13.port_b_address_width = 11,
		ram_block3a_13.port_b_data_out_clear = "none",
		ram_block3a_13.port_b_data_out_clock = "none",
		ram_block3a_13.port_b_data_width = 1,
		ram_block3a_13.port_b_first_address = 0,
		ram_block3a_13.port_b_first_bit_number = 13,
		ram_block3a_13.port_b_last_address = 2047,
		ram_block3a_13.port_b_logical_ram_depth = 2048,
		ram_block3a_13.port_b_logical_ram_width = 16,
		ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_13.ram_block_type = "auto",
		ram_block3a_13.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_14
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[14]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_14.connectivity_checking = "OFF",
		ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_14.operation_mode = "dual_port",
		ram_block3a_14.port_a_address_width = 11,
		ram_block3a_14.port_a_data_width = 1,
		ram_block3a_14.port_a_first_address = 0,
		ram_block3a_14.port_a_first_bit_number = 14,
		ram_block3a_14.port_a_last_address = 2047,
		ram_block3a_14.port_a_logical_ram_depth = 2048,
		ram_block3a_14.port_a_logical_ram_width = 16,
		ram_block3a_14.port_b_address_clear = "none",
		ram_block3a_14.port_b_address_clock = "clock1",
		ram_block3a_14.port_b_address_width = 11,
		ram_block3a_14.port_b_data_out_clear = "none",
		ram_block3a_14.port_b_data_out_clock = "none",
		ram_block3a_14.port_b_data_width = 1,
		ram_block3a_14.port_b_first_address = 0,
		ram_block3a_14.port_b_first_bit_number = 14,
		ram_block3a_14.port_b_last_address = 2047,
		ram_block3a_14.port_b_logical_ram_depth = 2048,
		ram_block3a_14.port_b_logical_ram_width = 16,
		ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_14.ram_block_type = "auto",
		ram_block3a_14.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_15
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[15]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_15.connectivity_checking = "OFF",
		ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_15.operation_mode = "dual_port",
		ram_block3a_15.port_a_address_width = 11,
		ram_block3a_15.port_a_data_width = 1,
		ram_block3a_15.port_a_first_address = 0,
		ram_block3a_15.port_a_first_bit_number = 15,
		ram_block3a_15.port_a_last_address = 2047,
		ram_block3a_15.port_a_logical_ram_depth = 2048,
		ram_block3a_15.port_a_logical_ram_width = 16,
		ram_block3a_15.port_b_address_clear = "none",
		ram_block3a_15.port_b_address_clock = "clock1",
		ram_block3a_15.port_b_address_width = 11,
		ram_block3a_15.port_b_data_out_clear = "none",
		ram_block3a_15.port_b_data_out_clock = "none",
		ram_block3a_15.port_b_data_width = 1,
		ram_block3a_15.port_b_first_address = 0,
		ram_block3a_15.port_b_first_bit_number = 15,
		ram_block3a_15.port_b_last_address = 2047,
		ram_block3a_15.port_b_logical_ram_depth = 2048,
		ram_block3a_15.port_b_logical_ram_width = 16,
		ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_15.ram_block_type = "auto",
		ram_block3a_15.lpm_type = "cyclone_ram_block";
	assign
		address_a_wire = address_a,
		address_b_wire = address_b,
		q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule //fifo_2k_altsyncram_6pl


//dffpipe DELAY=1 WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END

//synthesis_resources = lut 11 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  fifo_2k_dffpipe_ab3
	( 
	clock,
	clrn,
	d,
	q) /* synthesis synthesis_clearbox=1 */
		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
	input   clock;
	input   clrn;
	input   [10:0]  d;
	output   [10:0]  q;

	wire	[10:0]	wire_dffe4a_D;
	reg	[10:0]	dffe4a;
	wire ena;
	wire prn;
	wire sclr;

	// synopsys translate_off
	initial
		dffe4a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[0:0] <= wire_dffe4a_D[0:0];
	// synopsys translate_off
	initial
		dffe4a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[1:1] <= wire_dffe4a_D[1:1];
	// synopsys translate_off
	initial
		dffe4a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[2:2] <= wire_dffe4a_D[2:2];
	// synopsys translate_off
	initial
		dffe4a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[3:3] <= wire_dffe4a_D[3:3];
	// synopsys translate_off
	initial
		dffe4a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[4:4] <= wire_dffe4a_D[4:4];
	// synopsys translate_off
	initial
		dffe4a[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[5:5] <= wire_dffe4a_D[5:5];
	// synopsys translate_off
	initial
		dffe4a[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[6:6] <= wire_dffe4a_D[6:6];
	// synopsys translate_off
	initial
		dffe4a[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[7:7] <= wire_dffe4a_D[7:7];
	// synopsys translate_off
	initial
		dffe4a[8:8] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[8:8] <= wire_dffe4a_D[8:8];
	// synopsys translate_off
	initial
		dffe4a[9:9] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[9:9] <= wire_dffe4a_D[9:9];
	// synopsys translate_off
	initial
		dffe4a[10:10] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
		else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
		else if  (ena == 1'b1)   dffe4a[10:10] <= wire_dffe4a_D[10:10];
	assign
		wire_dffe4a_D = (d & {11{(~ sclr)}});
	assign
		ena = 1'b1,
		prn = 1'b1,
		q = dffe4a,
		sclr = 1'b0;
endmodule //fifo_2k_dffpipe_ab3


//dffpipe WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


//dffpipe WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END

//synthesis_resources = lut 11 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  fifo_2k_dffpipe_dm2
	( 
	clock,
	clrn,
	d,
	q) /* synthesis synthesis_clearbox=1 */
		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
	input   clock;
	input   clrn;
	input   [10:0]  d;
	output   [10:0]  q;

	wire	[10:0]	wire_dffe6a_D;
	reg	[10:0]	dffe6a;
	wire ena;
	wire prn;
	wire sclr;

	// synopsys translate_off
	initial
		dffe6a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
		else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
		else if  (ena == 1'b1)   dffe6a[0:0] <= wire_dffe6a_D[0:0];
	// synopsys translate_off
	initial
		dffe6a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
		else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
		else if  (ena == 1'b1)   dffe6a[1:1] <= wire_dffe6a_D[1:1];
	// synopsys translate_off
	initial
		dffe6a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
		else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
		else if  (ena == 1'b1)   dffe6a[2:2] <= wire_dffe6a_D[2:2];
	// synopsys translate_off
	initial
		dffe6a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
		else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
		else if  (ena == 1'b1)   dffe6a[3:3] <= wire_dffe6a_D[3:3];
	// synopsys translate_off
	initial
		dffe6a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
		else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
		else if  (ena == 1'b1)   dffe6a[4:4] <= wire_dffe6a_D[4:4];
	// synopsys translate_off
	initial
		dffe6a[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
		else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
		else if  (ena == 1'b1)   dffe6a[5:5] <= wire_dffe6a_D[5:5];
	// synopsys translate_off
	initial
		dffe6