fifo_2k.v

这是用python语言写的一个数字广播的信号处理工具包。利用它

	.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_3.connectivity_checking = "OFF",
		ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_3.operation_mode = "dual_port",
		ram_block3a_3.port_a_address_width = 11,
		ram_block3a_3.port_a_data_width = 1,
		ram_block3a_3.port_a_first_address = 0,
		ram_block3a_3.port_a_first_bit_number = 3,
		ram_block3a_3.port_a_last_address = 2047,
		ram_block3a_3.port_a_logical_ram_depth = 2048,
		ram_block3a_3.port_a_logical_ram_width = 16,
		ram_block3a_3.port_b_address_clear = "none",
		ram_block3a_3.port_b_address_clock = "clock1",
		ram_block3a_3.port_b_address_width = 11,
		ram_block3a_3.port_b_data_out_clear = "none",
		ram_block3a_3.port_b_data_out_clock = "none",
		ram_block3a_3.port_b_data_width = 1,
		ram_block3a_3.port_b_first_address = 0,
		ram_block3a_3.port_b_first_bit_number = 3,
		ram_block3a_3.port_b_last_address = 2047,
		ram_block3a_3.port_b_logical_ram_depth = 2048,
		ram_block3a_3.port_b_logical_ram_width = 16,
		ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_3.ram_block_type = "auto",
		ram_block3a_3.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_4
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[4]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_4.connectivity_checking = "OFF",
		ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_4.operation_mode = "dual_port",
		ram_block3a_4.port_a_address_width = 11,
		ram_block3a_4.port_a_data_width = 1,
		ram_block3a_4.port_a_first_address = 0,
		ram_block3a_4.port_a_first_bit_number = 4,
		ram_block3a_4.port_a_last_address = 2047,
		ram_block3a_4.port_a_logical_ram_depth = 2048,
		ram_block3a_4.port_a_logical_ram_width = 16,
		ram_block3a_4.port_b_address_clear = "none",
		ram_block3a_4.port_b_address_clock = "clock1",
		ram_block3a_4.port_b_address_width = 11,
		ram_block3a_4.port_b_data_out_clear = "none",
		ram_block3a_4.port_b_data_out_clock = "none",
		ram_block3a_4.port_b_data_width = 1,
		ram_block3a_4.port_b_first_address = 0,
		ram_block3a_4.port_b_first_bit_number = 4,
		ram_block3a_4.port_b_last_address = 2047,
		ram_block3a_4.port_b_logical_ram_depth = 2048,
		ram_block3a_4.port_b_logical_ram_width = 16,
		ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_4.ram_block_type = "auto",
		ram_block3a_4.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_5
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[5]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_5.connectivity_checking = "OFF",
		ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_5.operation_mode = "dual_port",
		ram_block3a_5.port_a_address_width = 11,
		ram_block3a_5.port_a_data_width = 1,
		ram_block3a_5.port_a_first_address = 0,
		ram_block3a_5.port_a_first_bit_number = 5,
		ram_block3a_5.port_a_last_address = 2047,
		ram_block3a_5.port_a_logical_ram_depth = 2048,
		ram_block3a_5.port_a_logical_ram_width = 16,
		ram_block3a_5.port_b_address_clear = "none",
		ram_block3a_5.port_b_address_clock = "clock1",
		ram_block3a_5.port_b_address_width = 11,
		ram_block3a_5.port_b_data_out_clear = "none",
		ram_block3a_5.port_b_data_out_clock = "none",
		ram_block3a_5.port_b_data_width = 1,
		ram_block3a_5.port_b_first_address = 0,
		ram_block3a_5.port_b_first_bit_number = 5,
		ram_block3a_5.port_b_last_address = 2047,
		ram_block3a_5.port_b_logical_ram_depth = 2048,
		ram_block3a_5.port_b_logical_ram_width = 16,
		ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_5.ram_block_type = "auto",
		ram_block3a_5.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_6
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[6]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_6.connectivity_checking = "OFF",
		ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_6.operation_mode = "dual_port",
		ram_block3a_6.port_a_address_width = 11,
		ram_block3a_6.port_a_data_width = 1,
		ram_block3a_6.port_a_first_address = 0,
		ram_block3a_6.port_a_first_bit_number = 6,
		ram_block3a_6.port_a_last_address = 2047,
		ram_block3a_6.port_a_logical_ram_depth = 2048,
		ram_block3a_6.port_a_logical_ram_width = 16,
		ram_block3a_6.port_b_address_clear = "none",
		ram_block3a_6.port_b_address_clock = "clock1",
		ram_block3a_6.port_b_address_width = 11,
		ram_block3a_6.port_b_data_out_clear = "none",
		ram_block3a_6.port_b_data_out_clock = "none",
		ram_block3a_6.port_b_data_width = 1,
		ram_block3a_6.port_b_first_address = 0,
		ram_block3a_6.port_b_first_bit_number = 6,
		ram_block3a_6.port_b_last_address = 2047,
		ram_block3a_6.port_b_logical_ram_depth = 2048,
		ram_block3a_6.port_b_logical_ram_width = 16,
		ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_6.ram_block_type = "auto",
		ram_block3a_6.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_7
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[7]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_7.connectivity_checking = "OFF",
		ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_7.operation_mode = "dual_port",
		ram_block3a_7.port_a_address_width = 11,
		ram_block3a_7.port_a_data_width = 1,
		ram_block3a_7.port_a_first_address = 0,
		ram_block3a_7.port_a_first_bit_number = 7,
		ram_block3a_7.port_a_last_address = 2047,
		ram_block3a_7.port_a_logical_ram_depth = 2048,
		ram_block3a_7.port_a_logical_ram_width = 16,
		ram_block3a_7.port_b_address_clear = "none",
		ram_block3a_7.port_b_address_clock = "clock1",
		ram_block3a_7.port_b_address_width = 11,
		ram_block3a_7.port_b_data_out_clear = "none",
		ram_block3a_7.port_b_data_out_clock = "none",
		ram_block3a_7.port_b_data_width = 1,
		ram_block3a_7.port_b_first_address = 0,
		ram_block3a_7.port_b_first_bit_number = 7,
		ram_block3a_7.port_b_last_address = 2047,
		ram_block3a_7.port_b_logical_ram_depth = 2048,
		ram_block3a_7.port_b_logical_ram_width = 16,
		ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_7.ram_block_type = "auto",
		ram_block3a_7.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_8
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[8]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_8.connectivity_checking = "OFF",
		ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_8.operation_mode = "dual_port",
		ram_block3a_8.port_a_address_width = 11,
		ram_block3a_8.port_a_data_width = 1,
		ram_block3a_8.port_a_first_address = 0,
		ram_block3a_8.port_a_first_bit_number = 8,
		ram_block3a_8.port_a_last_address = 2047,
		ram_block3a_8.port_a_logical_ram_depth = 2048,
		ram_block3a_8.port_a_logical_ram_width = 16,
		ram_block3a_8.port_b_address_clear = "none",
		ram_block3a_8.port_b_address_clock = "clock1",
		ram_block3a_8.port_b_address_width = 11,
		ram_block3a_8.port_b_data_out_clear = "none",
		ram_block3a_8.port_b_data_out_clock = "none",
		ram_block3a_8.port_b_data_width = 1,
		ram_block3a_8.port_b_first_address = 0,
		ram_block3a_8.port_b_first_bit_number = 8,
		ram_block3a_8.port_b_last_address = 2047,
		ram_block3a_8.port_b_logical_ram_depth = 2048,
		ram_block3a_8.port_b_logical_ram_width = 16,
		ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_8.ram_block_type = "auto",
		ram_block3a_8.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_9
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[9]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_9.connectivity_checking = "OFF",
		ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_9.operation_mode = "dual_port",
		ram_block3a_9.port_a_address_width = 11,
		ram_block3a_9.port_a_data_width = 1,
		ram_block3a_9.port_a_first_address = 0,
		ram_block3a_9.port_a_first_bit_number = 9,
		ram_block3a_9.port_a_last_address = 2047,
		ram_block3a_9.port_a_logical_ram_depth = 2048,
		ram_block3a_9.port_a_logical_ram_width = 16,
		ram_block3a_9.port_b_address_clear = "none",
		ram_block3a_9.port_b_address_clock = "clock1",
		ram_block3a_9.port_b_address_width = 11,
		ram_block3a_9.port_b_data_out_clear = "none",
		ram_block3a_9.port_b_data_out_clock = "none",
		ram_block3a_9.port_b_data_width = 1,
		ram_block3a_9.port_b_first_address = 0,
		ram_block3a_9.port_b_first_bit_number = 9,
		ram_block3a_9.port_b_last_address = 2047,
		ram_block3a_9.port_b_logical_ram_depth = 2048,
		ram_block3a_9.port_b_logical_ram_width = 16,
		ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_9.ram_block_type = "auto",
		ram_block3a_9.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_10
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[10]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),
	.portbdatain(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block3a_10.connectivity_checking = "OFF",
		ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
		ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
		ram_block3a_10.operation_mode = "dual_port",
		ram_block3a_10.port_a_address_width = 11,
		ram_block3a_10.port_a_data_width = 1,
		ram_block3a_10.port_a_first_address = 0,
		ram_block3a_10.port_a_first_bit_number = 10,
		ram_block3a_10.port_a_last_address = 2047,
		ram_block3a_10.port_a_logical_ram_depth = 2048,
		ram_block3a_10.port_a_logical_ram_width = 16,
		ram_block3a_10.port_b_address_clear = "none",
		ram_block3a_10.port_b_address_clock = "clock1",
		ram_block3a_10.port_b_address_width = 11,
		ram_block3a_10.port_b_data_out_clear = "none",
		ram_block3a_10.port_b_data_out_clock = "none",
		ram_block3a_10.port_b_data_width = 1,
		ram_block3a_10.port_b_first_address = 0,
		ram_block3a_10.port_b_first_bit_number = 10,
		ram_block3a_10.port_b_last_address = 2047,
		ram_block3a_10.port_b_logical_ram_depth = 2048,
		ram_block3a_10.port_b_logical_ram_width = 16,
		ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
		ram_block3a_10.ram_block_type = "auto",
		ram_block3a_10.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block3a_11
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[10:0]}),
	.portadatain({data_a[11]}),
	.portadataout(),
	.portawe(1'b1),
	.portbaddr({address_b_wire[10:0]}),
	.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.portabyteenamasks(1'b1),
	.portbbyteenamasks(1'b1),