📄 fifo_2k.v

📁 这是用python语言写的一个数字广播的信号处理工具包。利用它
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	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_6.cin_used = "true",		countera_6.lut_mask = "6c50",		countera_6.operation_mode = "arithmetic",		countera_6.sum_lutc_input = "cin",		countera_6.synch_mode = "on",		countera_6.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_7	( 	.aclr(aclr),	.cin(wire_countera_6cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_7cout[0:0]),	.dataa(power_modified_counter_values[6]),	.datab(power_modified_counter_values[7]),	.ena(1'b1),	.regout(wire_countera_regout[7:7]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_7.cin_used = "true",		countera_7.lut_mask = "6c50",		countera_7.operation_mode = "arithmetic",		countera_7.sum_lutc_input = "cin",		countera_7.synch_mode = "on",		countera_7.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_8	( 	.aclr(aclr),	.cin(wire_countera_7cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_8cout[0:0]),	.dataa(power_modified_counter_values[7]),	.datab(power_modified_counter_values[8]),	.ena(1'b1),	.regout(wire_countera_regout[8:8]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_8.cin_used = "true",		countera_8.lut_mask = "6c50",		countera_8.operation_mode = "arithmetic",		countera_8.sum_lutc_input = "cin",		countera_8.synch_mode = "on",		countera_8.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_9	( 	.aclr(aclr),	.cin(wire_countera_8cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_9cout[0:0]),	.dataa(power_modified_counter_values[8]),	.datab(power_modified_counter_values[9]),	.ena(1'b1),	.regout(wire_countera_regout[9:9]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_9.cin_used = "true",		countera_9.lut_mask = "6c50",		countera_9.operation_mode = "arithmetic",		countera_9.sum_lutc_input = "cin",		countera_9.synch_mode = "on",		countera_9.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_10	( 	.aclr(aclr),	.cin(wire_countera_9cout[0:0]),	.clk(clock),	.combout(),	.cout(),	.dataa(power_modified_counter_values[10]),	.ena(1'b1),	.regout(wire_countera_regout[10:10]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datab(1'b1),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_10.cin_used = "true",		countera_10.lut_mask = "5a5a",		countera_10.operation_mode = "normal",		countera_10.sum_lutc_input = "cin",		countera_10.synch_mode = "on",		countera_10.lpm_type = "cyclone_lcell";	cyclone_lcell   parity	( 	.aclr(aclr),	.cin(updown),	.clk(clock),	.combout(),	.cout(wire_parity_cout),	.dataa(cnt_en),	.datab((~ wire_parity_regout)),	.ena(1'b1),	.regout(wire_parity_regout),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		parity.cin_used = "true",		parity.lut_mask = "9982",		parity.operation_mode = "arithmetic",		parity.synch_mode = "on",		parity.lpm_type = "cyclone_lcell";	assign		power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])},		q = power_modified_counter_values,		sclr = 1'b0,		updown = 1'b1;endmodule //fifo_2k_a_graycounter_2r6//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END//synthesis_resources = M4K 8 //synopsys translate_off`timescale 1 ps / 1 ps//synopsys translate_onmodule  fifo_2k_altsyncram_6pl	( 	address_a,	address_b,	clock0,	clock1,	clocken1,	data_a,	q_b,	wren_a) /* synthesis synthesis_clearbox=1 */;	input   [10:0]  address_a;	input   [10:0]  address_b;	input   clock0;	input   clock1;	input   clocken1;	input   [15:0]  data_a;	output   [15:0]  q_b;	input   wren_a;	wire  [0:0]   wire_ram_block3a_0portbdataout;	wire  [0:0]   wire_ram_block3a_1portbdataout;	wire  [0:0]   wire_ram_block3a_2portbdataout;	wire  [0:0]   wire_ram_block3a_3portbdataout;	wire  [0:0]   wire_ram_block3a_4portbdataout;	wire  [0:0]   wire_ram_block3a_5portbdataout;	wire  [0:0]   wire_ram_block3a_6portbdataout;	wire  [0:0]   wire_ram_block3a_7portbdataout;	wire  [0:0]   wire_ram_block3a_8portbdataout;	wire  [0:0]   wire_ram_block3a_9portbdataout;	wire  [0:0]   wire_ram_block3a_10portbdataout;	wire  [0:0]   wire_ram_block3a_11portbdataout;	wire  [0:0]   wire_ram_block3a_12portbdataout;	wire  [0:0]   wire_ram_block3a_13portbdataout;	wire  [0:0]   wire_ram_block3a_14portbdataout;	wire  [0:0]   wire_ram_block3a_15portbdataout;	wire  [10:0]  address_a_wire;	wire  [10:0]  address_b_wire;	cyclone_ram_block   ram_block3a_0	( 	.clk0(clock0),	.clk1(clock1),	.ena0(wren_a),	.ena1(clocken1),	.portaaddr({address_a_wire[10:0]}),	.portadatain({data_a[0]}),	.portadataout(),	.portawe(1'b1),	.portbaddr({address_b_wire[10:0]}),	.portbdataout(wire_ram_block3a_0portbdataout[0:0]),	.portbrewe(1'b1)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.clr0(1'b0),	.clr1(1'b0),	.portabyteenamasks(1'b1),	.portbbyteenamasks(1'b1),	.portbdatain(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		ram_block3a_0.connectivity_checking = "OFF",		ram_block3a_0.logical_ram_name = "ALTSYNCRAM",		ram_block3a_0.mixed_port_feed_through_mode = "dont_care",		ram_block3a_0.operation_mode = "dual_port",		ram_block3a_0.port_a_address_width = 11,		ram_block3a_0.port_a_data_width = 1,		ram_block3a_0.port_a_first_address = 0,		ram_block3a_0.port_a_first_bit_number = 0,		ram_block3a_0.port_a_last_address = 2047,		ram_block3a_0.port_a_logical_ram_depth = 2048,		ram_block3a_0.port_a_logical_ram_width = 16,		ram_block3a_0.port_b_address_clear = "none",		ram_block3a_0.port_b_address_clock = "clock1",		ram_block3a_0.port_b_address_width = 11,		ram_block3a_0.port_b_data_out_clear = "none",		ram_block3a_0.port_b_data_out_clock = "none",		ram_block3a_0.port_b_data_width = 1,		ram_block3a_0.port_b_first_address = 0,		ram_block3a_0.port_b_first_bit_number = 0,		ram_block3a_0.port_b_last_address = 2047,		ram_block3a_0.port_b_logical_ram_depth = 2048,		ram_block3a_0.port_b_logical_ram_width = 16,		ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",		ram_block3a_0.ram_block_type = "auto",		ram_block3a_0.lpm_type = "cyclone_ram_block";	cyclone_ram_block   ram_block3a_1	( 	.clk0(clock0),	.clk1(clock1),	.ena0(wren_a),	.ena1(clocken1),	.portaaddr({address_a_wire[10:0]}),	.portadatain({data_a[1]}),	.portadataout(),	.portawe(1'b1),	.portbaddr({address_b_wire[10:0]}),	.portbdataout(wire_ram_block3a_1portbdataout[0:0]),	.portbrewe(1'b1)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.clr0(1'b0),	.clr1(1'b0),	.portabyteenamasks(1'b1),	.portbbyteenamasks(1'b1),	.portbdatain(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		ram_block3a_1.connectivity_checking = "OFF",		ram_block3a_1.logical_ram_name = "ALTSYNCRAM",		ram_block3a_1.mixed_port_feed_through_mode = "dont_care",		ram_block3a_1.operation_mode = "dual_port",		ram_block3a_1.port_a_address_width = 11,		ram_block3a_1.port_a_data_width = 1,		ram_block3a_1.port_a_first_address = 0,		ram_block3a_1.port_a_first_bit_number = 1,		ram_block3a_1.port_a_last_address = 2047,		ram_block3a_1.port_a_logical_ram_depth = 2048,		ram_block3a_1.port_a_logical_ram_width = 16,		ram_block3a_1.port_b_address_clear = "none",		ram_block3a_1.port_b_address_clock = "clock1",		ram_block3a_1.port_b_address_width = 11,		ram_block3a_1.port_b_data_out_clear = "none",		ram_block3a_1.port_b_data_out_clock = "none",		ram_block3a_1.port_b_data_width = 1,		ram_block3a_1.port_b_first_address = 0,		ram_block3a_1.port_b_first_bit_number = 1,		ram_block3a_1.port_b_last_address = 2047,		ram_block3a_1.port_b_logical_ram_depth = 2048,		ram_block3a_1.port_b_logical_ram_width = 16,		ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",		ram_block3a_1.ram_block_type = "auto",		ram_block3a_1.lpm_type = "cyclone_ram_block";	cyclone_ram_block   ram_block3a_2	( 	.clk0(clock0),	.clk1(clock1),	.ena0(wren_a),	.ena1(clocken1),	.portaaddr({address_a_wire[10:0]}),	.portadatain({data_a[2]}),	.portadataout(),	.portawe(1'b1),	.portbaddr({address_b_wire[10:0]}),	.portbdataout(wire_ram_block3a_2portbdataout[0:0]),	.portbrewe(1'b1)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.clr0(1'b0),	.clr1(1'b0),	.portabyteenamasks(1'b1),	.portbbyteenamasks(1'b1),	.portbdatain(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		ram_block3a_2.connectivity_checking = "OFF",		ram_block3a_2.logical_ram_name = "ALTSYNCRAM",		ram_block3a_2.mixed_port_feed_through_mode = "dont_care",		ram_block3a_2.operation_mode = "dual_port",		ram_block3a_2.port_a_address_width = 11,		ram_block3a_2.port_a_data_width = 1,		ram_block3a_2.port_a_first_address = 0,		ram_block3a_2.port_a_first_bit_number = 2,		ram_block3a_2.port_a_last_address = 2047,		ram_block3a_2.port_a_logical_ram_depth = 2048,		ram_block3a_2.port_a_logical_ram_width = 16,		ram_block3a_2.port_b_address_clear = "none",		ram_block3a_2.port_b_address_clock = "clock1",		ram_block3a_2.port_b_address_width = 11,		ram_block3a_2.port_b_data_out_clear = "none",		ram_block3a_2.port_b_data_out_clock = "none",		ram_block3a_2.port_b_data_width = 1,		ram_block3a_2.port_b_first_address = 0,		ram_block3a_2.port_b_first_bit_number = 2,		ram_block3a_2.port_b_last_address = 2047,		ram_block3a_2.port_b_logical_ram_depth = 2048,		ram_block3a_2.port_b_logical_ram_width = 16,		ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",		ram_block3a_2.ram_block_type = "auto",		ram_block3a_2.lpm_type = "cyclone_ram_block";	cyclone_ram_block   ram_block3a_3	( 	.clk0(clock0),	.clk1(clock1),	.ena0(wren_a),	.ena1(clocken1),	.portaaddr({address_a_wire[10:0]}),	.portadatain({data_a[3]}),	.portadataout(),	.portawe(1'b1),	.portbaddr({address_b_wire[10:0]}),
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