📄 fifo_2k.v

📁 这是用python语言写的一个数字广播的信号处理工具包。利用它
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	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_8.cin_used = "true",		countera_8.lut_mask = "6c50",		countera_8.operation_mode = "arithmetic",		countera_8.sum_lutc_input = "cin",		countera_8.synch_mode = "on",		countera_8.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_9	( 	.aclr(aclr),	.cin(wire_countera_8cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_9cout[0:0]),	.dataa(power_modified_counter_values[8]),	.datab(power_modified_counter_values[9]),	.ena(1'b1),	.regout(wire_countera_regout[9:9]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_9.cin_used = "true",		countera_9.lut_mask = "6c50",		countera_9.operation_mode = "arithmetic",		countera_9.sum_lutc_input = "cin",		countera_9.synch_mode = "on",		countera_9.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_10	( 	.aclr(aclr),	.cin(wire_countera_9cout[0:0]),	.clk(clock),	.combout(),	.cout(),	.dataa(power_modified_counter_values[10]),	.ena(1'b1),	.regout(wire_countera_regout[10:10]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datab(1'b1),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_10.cin_used = "true",		countera_10.lut_mask = "5a5a",		countera_10.operation_mode = "normal",		countera_10.sum_lutc_input = "cin",		countera_10.synch_mode = "on",		countera_10.lpm_type = "cyclone_lcell";	cyclone_lcell   parity	( 	.aclr(aclr),	.cin(updown),	.clk(clock),	.combout(),	.cout(wire_parity_cout),	.dataa(cnt_en),	.datab(wire_parity_regout),	.ena(1'b1),	.regout(wire_parity_regout),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		parity.cin_used = "true",		parity.lut_mask = "6682",		parity.operation_mode = "arithmetic",		parity.synch_mode = "on",		parity.lpm_type = "cyclone_lcell";	assign		power_modified_counter_values = {wire_countera_regout[10:0]},		q = power_modified_counter_values,		sclr = 1'b0,		updown = 1'b1;endmodule //fifo_2k_a_graycounter_726//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END//synthesis_resources = lut 12 //synopsys translate_off`timescale 1 ps / 1 ps//synopsys translate_onmodule  fifo_2k_a_graycounter_2r6	( 	aclr,	clock,	cnt_en,	q) /* synthesis synthesis_clearbox=1 */;	input   aclr;	input   clock;	input   cnt_en;	output   [10:0]  q;	wire  [0:0]   wire_countera_0cout;	wire  [0:0]   wire_countera_1cout;	wire  [0:0]   wire_countera_2cout;	wire  [0:0]   wire_countera_3cout;	wire  [0:0]   wire_countera_4cout;	wire  [0:0]   wire_countera_5cout;	wire  [0:0]   wire_countera_6cout;	wire  [0:0]   wire_countera_7cout;	wire  [0:0]   wire_countera_8cout;	wire  [0:0]   wire_countera_9cout;	wire  [10:0]   wire_countera_regout;	wire  wire_parity_cout;	wire  wire_parity_regout;	wire  [10:0]  power_modified_counter_values;	wire sclr;	wire updown;	cyclone_lcell   countera_0	( 	.aclr(aclr),	.cin(wire_parity_cout),	.clk(clock),	.combout(),	.cout(wire_countera_0cout[0:0]),	.dataa(cnt_en),	.datab(wire_countera_regout[0:0]),	.ena(1'b1),	.regout(wire_countera_regout[0:0]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_0.cin_used = "true",		countera_0.lut_mask = "c6a0",		countera_0.operation_mode = "arithmetic",		countera_0.sum_lutc_input = "cin",		countera_0.synch_mode = "on",		countera_0.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_1	( 	.aclr(aclr),	.cin(wire_countera_0cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_1cout[0:0]),	.dataa(power_modified_counter_values[0]),	.datab(power_modified_counter_values[1]),	.ena(1'b1),	.regout(wire_countera_regout[1:1]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_1.cin_used = "true",		countera_1.lut_mask = "6c50",		countera_1.operation_mode = "arithmetic",		countera_1.sum_lutc_input = "cin",		countera_1.synch_mode = "on",		countera_1.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_2	( 	.aclr(aclr),	.cin(wire_countera_1cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_2cout[0:0]),	.dataa(power_modified_counter_values[1]),	.datab(power_modified_counter_values[2]),	.ena(1'b1),	.regout(wire_countera_regout[2:2]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_2.cin_used = "true",		countera_2.lut_mask = "6c50",		countera_2.operation_mode = "arithmetic",		countera_2.sum_lutc_input = "cin",		countera_2.synch_mode = "on",		countera_2.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_3	( 	.aclr(aclr),	.cin(wire_countera_2cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_3cout[0:0]),	.dataa(power_modified_counter_values[2]),	.datab(power_modified_counter_values[3]),	.ena(1'b1),	.regout(wire_countera_regout[3:3]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_3.cin_used = "true",		countera_3.lut_mask = "6c50",		countera_3.operation_mode = "arithmetic",		countera_3.sum_lutc_input = "cin",		countera_3.synch_mode = "on",		countera_3.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_4	( 	.aclr(aclr),	.cin(wire_countera_3cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_4cout[0:0]),	.dataa(power_modified_counter_values[3]),	.datab(power_modified_counter_values[4]),	.ena(1'b1),	.regout(wire_countera_regout[4:4]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_4.cin_used = "true",		countera_4.lut_mask = "6c50",		countera_4.operation_mode = "arithmetic",		countera_4.sum_lutc_input = "cin",		countera_4.synch_mode = "on",		countera_4.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_5	( 	.aclr(aclr),	.cin(wire_countera_4cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_5cout[0:0]),	.dataa(power_modified_counter_values[4]),	.datab(power_modified_counter_values[5]),	.ena(1'b1),	.regout(wire_countera_regout[5:5]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),	.regcascin(1'b0),	.sload(1'b0)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_on	`endif	// synopsys translate_off	,	.cin0(),	.cin1(),	.cout0(),	.cout1(),	.devclrn(),	.devpor()	// synopsys translate_on	);	defparam		countera_5.cin_used = "true",		countera_5.lut_mask = "6c50",		countera_5.operation_mode = "arithmetic",		countera_5.sum_lutc_input = "cin",		countera_5.synch_mode = "on",		countera_5.lpm_type = "cyclone_lcell";	cyclone_lcell   countera_6	( 	.aclr(aclr),	.cin(wire_countera_5cout[0:0]),	.clk(clock),	.combout(),	.cout(wire_countera_6cout[0:0]),	.dataa(power_modified_counter_values[5]),	.datab(power_modified_counter_values[6]),	.ena(1'b1),	.regout(wire_countera_regout[6:6]),	.sclr(sclr)	`ifdef FORMAL_VERIFICATION	`else	// synopsys translate_off	`endif	,	.aload(1'b0),	.datac(1'b1),	.datad(1'b1),	.inverta(1'b0),
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