sub32.v

这是用python语言写的一个数字广播的信号处理工具包。利用它

	.ena(clken),
	.regout(wire_add_sub_cella_regout[15:15]));
	defparam
		add_sub_cella_15.cin_used = "true",
		add_sub_cella_15.lut_mask = "69b2",
		add_sub_cella_15.operation_mode = "arithmetic",
		add_sub_cella_15.sum_lutc_input = "cin",
		add_sub_cella_15.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_16
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_15cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_16cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[16:16]),
	.datab(wire_add_sub_cella_datab[16:16]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[16:16]));
	defparam
		add_sub_cella_16.cin_used = "true",
		add_sub_cella_16.lut_mask = "69b2",
		add_sub_cella_16.operation_mode = "arithmetic",
		add_sub_cella_16.sum_lutc_input = "cin",
		add_sub_cella_16.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_17
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_16cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_17cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[17:17]),
	.datab(wire_add_sub_cella_datab[17:17]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[17:17]));
	defparam
		add_sub_cella_17.cin_used = "true",
		add_sub_cella_17.lut_mask = "69b2",
		add_sub_cella_17.operation_mode = "arithmetic",
		add_sub_cella_17.sum_lutc_input = "cin",
		add_sub_cella_17.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_18
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_17cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_18cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[18:18]),
	.datab(wire_add_sub_cella_datab[18:18]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[18:18]));
	defparam
		add_sub_cella_18.cin_used = "true",
		add_sub_cella_18.lut_mask = "69b2",
		add_sub_cella_18.operation_mode = "arithmetic",
		add_sub_cella_18.sum_lutc_input = "cin",
		add_sub_cella_18.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_19
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_18cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_19cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[19:19]),
	.datab(wire_add_sub_cella_datab[19:19]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[19:19]));
	defparam
		add_sub_cella_19.cin_used = "true",
		add_sub_cella_19.lut_mask = "69b2",
		add_sub_cella_19.operation_mode = "arithmetic",
		add_sub_cella_19.sum_lutc_input = "cin",
		add_sub_cella_19.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_20
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_19cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_20cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[20:20]),
	.datab(wire_add_sub_cella_datab[20:20]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[20:20]));
	defparam
		add_sub_cella_20.cin_used = "true",
		add_sub_cella_20.lut_mask = "69b2",
		add_sub_cella_20.operation_mode = "arithmetic",
		add_sub_cella_20.sum_lutc_input = "cin",
		add_sub_cella_20.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_21
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_20cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_21cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[21:21]),
	.datab(wire_add_sub_cella_datab[21:21]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[21:21]));
	defparam
		add_sub_cella_21.cin_used = "true",
		add_sub_cella_21.lut_mask = "69b2",
		add_sub_cella_21.operation_mode = "arithmetic",
		add_sub_cella_21.sum_lutc_input = "cin",
		add_sub_cella_21.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_22
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_21cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_22cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[22:22]),
	.datab(wire_add_sub_cella_datab[22:22]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[22:22]));
	defparam
		add_sub_cella_22.cin_used = "true",
		add_sub_cella_22.lut_mask = "69b2",
		add_sub_cella_22.operation_mode = "arithmetic",
		add_sub_cella_22.sum_lutc_input = "cin",
		add_sub_cella_22.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_23
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_22cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_23cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[23:23]),
	.datab(wire_add_sub_cella_datab[23:23]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[23:23]));
	defparam
		add_sub_cella_23.cin_used = "true",
		add_sub_cella_23.lut_mask = "69b2",
		add_sub_cella_23.operation_mode = "arithmetic",
		add_sub_cella_23.sum_lutc_input = "cin",
		add_sub_cella_23.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_24
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_23cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_24cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[24:24]),
	.datab(wire_add_sub_cella_datab[24:24]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[24:24]));
	defparam
		add_sub_cella_24.cin_used = "true",
		add_sub_cella_24.lut_mask = "69b2",
		add_sub_cella_24.operation_mode = "arithmetic",
		add_sub_cella_24.sum_lutc_input = "cin",
		add_sub_cella_24.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_25
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_24cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_25cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[25:25]),
	.datab(wire_add_sub_cella_datab[25:25]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[25:25]));
	defparam
		add_sub_cella_25.cin_used = "true",
		add_sub_cella_25.lut_mask = "69b2",
		add_sub_cella_25.operation_mode = "arithmetic",
		add_sub_cella_25.sum_lutc_input = "cin",
		add_sub_cella_25.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_26
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_25cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_26cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[26:26]),
	.datab(wire_add_sub_cella_datab[26:26]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[26:26]));
	defparam
		add_sub_cella_26.cin_used = "true",
		add_sub_cella_26.lut_mask = "69b2",
		add_sub_cella_26.operation_mode = "arithmetic",
		add_sub_cella_26.sum_lutc_input = "cin",
		add_sub_cella_26.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_27
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_26cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_27cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[27:27]),
	.datab(wire_add_sub_cella_datab[27:27]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[27:27]));
	defparam
		add_sub_cella_27.cin_used = "true",
		add_sub_cella_27.lut_mask = "69b2",
		add_sub_cella_27.operation_mode = "arithmetic",
		add_sub_cella_27.sum_lutc_input = "cin",
		add_sub_cella_27.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_28
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_27cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_28cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[28:28]),
	.datab(wire_add_sub_cella_datab[28:28]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[28:28]));
	defparam
		add_sub_cella_28.cin_used = "true",
		add_sub_cella_28.lut_mask = "69b2",
		add_sub_cella_28.operation_mode = "arithmetic",
		add_sub_cella_28.sum_lutc_input = "cin",
		add_sub_cella_28.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_29
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_28cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_29cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[29:29]),
	.datab(wire_add_sub_cella_datab[29:29]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[29:29]));
	defparam
		add_sub_cella_29.cin_used = "true",
		add_sub_cella_29.lut_mask = "69b2",
		add_sub_cella_29.operation_mode = "arithmetic",
		add_sub_cella_29.sum_lutc_input = "cin",
		add_sub_cella_29.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_30
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_29cout[0:0]),
	.clk(clock),
	.cout(wire_add_sub_cella_30cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[30:30]),
	.datab(wire_add_sub_cella_datab[30:30]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[30:30]));
	defparam
		add_sub_cella_30.cin_used = "true",
		add_sub_cella_30.lut_mask = "69b2",
		add_sub_cella_30.operation_mode = "arithmetic",
		add_sub_cella_30.sum_lutc_input = "cin",
		add_sub_cella_30.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_31
	( 
	.aclr(aclr),
	.cin(wire_add_sub_cella_30cout[0:0]),
	.clk(clock),
	.dataa(wire_add_sub_cella_dataa[31:31]),
	.datab(wire_add_sub_cella_datab[31:31]),
	.ena(clken),
	.regout(wire_add_sub_cella_regout[31:31]));
	defparam
		add_sub_cella_31.cin_used = "true",
		add_sub_cella_31.lut_mask = "6969",
		add_sub_cella_31.operation_mode = "normal",
		add_sub_cella_31.sum_lutc_input = "cin",
		add_sub_cella_31.lpm_type = "stratix_lcell";
	assign
		wire_add_sub_cella_dataa = dataa,
		wire_add_sub_cella_datab = datab;
	assign
		result = wire_add_sub_cella_regout;
endmodule //sub32_add_sub_cqa
//VALID FILE


module sub32 (
	dataa,
	datab,
	clock,
	aclr,
	clken,
	result)/* synthesis synthesis_clearbox = 1 */;

	input	[31:0]  dataa;
	input	[31:0]  datab;
	input	  clock;
	input	  aclr;
	input	  clken;
	output	[31:0]  result;

	wire [31:0] sub_wire0;
	wire [31:0] result = sub_wire0[31:0];

	sub32_add_sub_cqa	sub32_add_sub_cqa_component (
				.dataa (dataa),
				.datab (datab),
				.clken (clken),
				.aclr (aclr),
				.clock (clock),
				.result (sub_wire0));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "32"
// Retrieval info: PRIVATE: Function NUMERIC "1"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "1"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all