db_wbx.py

这是用python语言写的一个数字广播的信号处理工具包。利用它

#
# Copyright 2007 Free Software Foundation, Inc.
# 
# This file is part of GNU Radio
# 
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
# 
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
# 
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING.  If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
# 

from gnuradio import usrp1
import time,math

from usrpm import usrp_dbid
import db_base
import db_instantiator
from usrpm.usrp_fpga_regs import *

#debug_using_gui = True                  # Must be set to True or False
debug_using_gui = False                  # Must be set to True or False

#if debug_using_gui:
#    import flexrf_debug_gui

# d'board i/o pin defs

# TX IO Pins
TX_POWER = (1 << 0)         # TX Side Power
RX_TXN = (1 << 1)           # T/R antenna switch for TX/RX port

# RX IO Pins
RX2_RX1N = (1 << 0)         # antenna switch between RX2 and TX/RX port
RXENABLE = (1 << 1)         # enables mixer
PLL_LOCK_DETECT = (1 << 2)  # Muxout pin from PLL -- MUST BE INPUT
MReset = (1 << 3)           # NB6L239 Master Reset, asserted low
SELA0 = (1 << 4)            # NB6L239 SelA0
SELA1 = (1 << 5)            # NB6L239 SelA1
SELB0 = (1 << 6)            # NB6L239 SelB0
SELB1 = (1 << 7)            # NB6L239 SelB1
PLL_ENABLE = (1 << 8)       # CE Pin on PLL
AUX_SCLK = (1 << 9)         # ALT SPI SCLK
AUX_SDO = (1 << 10)         # ALT SPI SDO
AUX_SEN = (1 << 11)         # ALT SPI SEN

SPI_ENABLE_TX_A = usrp1.SPI_ENABLE_TX_A
SPI_ENABLE_TX_B = usrp1.SPI_ENABLE_TX_B
SPI_ENABLE_RX_A = usrp1.SPI_ENABLE_RX_A
SPI_ENABLE_RX_B = usrp1.SPI_ENABLE_RX_B


"""
A few comments about the WBX boards:
  They are half-duplex.  I.e., transmit and receive are mutually exclusive.
  There is a single LO for both the Tx and Rx sides.
  The the shared control signals are hung off of the Rx side.
  The shared io controls are duplexed onto the Rx side pins.
  The wbx_high d'board always needs to be in 'auto_tr_mode'
"""


class wbx_base(db_base.db_base):
    """
    Abstract base class for all wbx boards.

    Derive board specific subclasses from db_wbx_base_{tx,rx}
    """
    def __init__(self, usrp, which):
        """
        @param usrp: instance of usrp.source_c
        @param which: which side: 0 or 1 corresponding to side A or B respectively
        @type which: int
        """
        # sets _u  _which _tx and _slot
        db_base.db_base.__init__(self, usrp, which)

        self.first = True
        self.spi_format = usrp1.SPI_FMT_MSB | usrp1.SPI_FMT_HDR_0

        # FIXME -- the write reg functions don't work with 0xffff for masks
        self._rx_write_oe(int(PLL_ENABLE|MReset|SELA0|SELA1|SELB0|SELB1|RX2_RX1N|RXENABLE), 0x7fff)
        self._rx_write_io((PLL_ENABLE|MReset|0|RXENABLE), (PLL_ENABLE|MReset|RX2_RX1N|RXENABLE))

        self._tx_write_oe((TX_POWER|RX_TXN), 0x7fff)
        self._tx_write_io((0|RX_TXN), (TX_POWER|RX_TXN))  # TX off, TR switch set to RX

        self.spi_enable = (SPI_ENABLE_RX_A, SPI_ENABLE_RX_B)[which]

        self.set_auto_tr(False)
        
        #if debug_using_gui:
        #    title = "FlexRF Debug Rx"
        #    if self._tx:
        #        title = "FlexRF Debug Tx"
        #    self.gui = flexrf_debug_gui.flexrf_debug_gui(self, title)
        #    self.gui.Show(True)


    def __del__(self):
        #self._u.write_io(self._which, self.power_off, POWER_UP)   # turn off power to board
        #self._u._write_oe(self._which, 0, 0xffff)   # turn off all outputs
        self.set_auto_tr(False)

    def _lock_detect(self):
        """
        @returns: the value of the VCO/PLL lock detect bit.
        @rtype: 0 or 1
        """
        if self._rx_read_io() & PLL_LOCK_DETECT:
            return True
        else:      # Give it a second chance
            if self._rx_read_io() & PLL_LOCK_DETECT:
                return True
            else:
                return False
        
    # Both sides need access to the Rx pins.
    # Write them directly, bypassing the convenience routines.
    # (Sort of breaks modularity, but will work...)

    def _tx_write_oe(self, value, mask):
        return self._u._write_fpga_reg((FR_OE_0, FR_OE_2)[self._which],
                                       ((mask & 0xffff) << 16) | (value & 0xffff))

    def _rx_write_oe(self, value, mask):
        return self._u._write_fpga_reg((FR_OE_1, FR_OE_3)[self._which],
                                       ((mask & 0xffff) << 16) | (value & 0xffff))

    def _tx_write_io(self, value, mask):
        return self._u._write_fpga_reg((FR_IO_0, FR_IO_2)[self._which],
                                       ((mask & 0xffff) << 16) | (value & 0xffff))

    def _rx_write_io(self, value, mask):
        return self._u._write_fpga_reg((FR_IO_1, FR_IO_3)[self._which],
                                       ((mask & 0xffff) << 16) | (value & 0xffff))

    def _rx_read_io(self):
        t = self._u._read_fpga_reg((FR_RB_IO_RX_A_IO_TX_A, FR_RB_IO_RX_B_IO_TX_B)[self._which])
        return (t >> 16) & 0xffff

    def _tx_read_io(self):
        t = self._u._read_fpga_reg((FR_RB_IO_RX_A_IO_TX_A, FR_RB_IO_RX_B_IO_TX_B)[self._which])
        return t & 0xffff


    def _compute_regs(self, freq):
        """
        Determine values of registers, along with actual freq.
        
        @param freq: target frequency in Hz
        @type freq: float
        @returns: (R, N, func, init, actual_freq)
        @rtype: tuple(int, int, int, int, float)
        
        Override this in derived classes.
        """
        raise NotImplementedError

    def _refclk_freq(self):
        return float(self._u.fpga_master_clock_freq())/self._refclk_divisor()

    def _refclk_divisor(self):
        """
        Return value to stick in REFCLK_DIVISOR register
        """
        return 1
    
    # ----------------------------------------------------------------
    
    def set_freq(self, freq):
        """
        @returns (ok, actual_baseband_freq) where:
           ok is True or False and indicates success or failure,
           actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
        """
        raise NotImplementedError

    def gain_range(self):
        """
        Return range of gain that can be set by this d'board.

        @returns (min_gain, max_gain, step_size)
        Where gains are expressed in decibels (your mileage may vary)
        """
        raise NotImplementedError

    def set_gain(self, gain):
        """
        Set the gain.

        @param gain:  gain in decibels
        @returns True/False
        """
        raise NotImplementedError

    def _set_pga(self, pga_gain):
        if(self._which == 0):
            self._u.set_pga (0, pga_gain)
            self._u.set_pga (1, pga_gain)
        else:
            self._u.set_pga (2, pga_gain)
            self._u.set_pga (3, pga_gain)

    def is_quadrature(self):
        """
        Return True if this board requires both I & Q analog channels.

        This bit of info is useful when setting up the USRP Rx mux register.
        """
        return True

# ----------------------------------------------------------------

class wbx_base_tx(wbx_base):
    def __init__(self, usrp, which):
        """
        @param usrp: instance of usrp.sink_c
        @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
        """
        wbx_base.__init__(self, usrp, which)

        # power up the transmit side, NO -- but set antenna to receive
        self._u.write_io(self._which, (TX_POWER), (TX_POWER|RX_TXN))
        self._lo_offset = 0e6

        #  Gain is not set by the PGA, but the PGA must be set at max gain in the TX
        return self._set_pga(self._u.pga_max())

    def __del__(self):
        # Power down and leave the T/R switch in the R position
        self._u.write_io(self._which, (RX_TXN), (TX_POWER|RX_TXN))
        wbx_base.__del__(self)

    def set_auto_tr(self, on):
        if on:
            self.set_atr_mask (RX_TXN)
            self.set_atr_txval(0)
            self.set_atr_rxval(RX_TXN)
        else:
            self.set_atr_mask (0)
            self.set_atr_txval(0)
            self.set_atr_rxval(0)

    def set_enable(self, on):
        """
        Enable transmitter if on is True
        """
        if on:
            v = 0
        else:
            v = RX_TXN
        self._u.write_io(self._which, v, RX_TXN)

    def set_lo_offset(self, offset):
	"""
	Set amount by which LO is offset from requested tuning frequency.
	
	@param offset: offset in Hz
	"""
	self._lo_offset = offset

    def lo_offset(self):
	"""
	Get amount by which LO is offset from requested tuning frequency.
	
	@returns Offset in Hz
	"""
	return self._lo_offset
	
class wbx_base_rx(wbx_base):
    def __init__(self, usrp, which):
        """
        @param usrp: instance of usrp.source_c
        @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
        """
        wbx_base.__init__(self, usrp, which)
        
        # set up for RX on TX/RX port
        self.select_rx_antenna('TX/RX')

        self.bypass_adc_buffers(True)

        self._lo_offset = -4e6

    def __del__(self):
        # Power down
        self._u.write_io(self._which, 0, (RXENABLE))
        wbx_base.__del__(self)
    
    def set_auto_tr(self, on):
        if on:
            self.set_atr_mask (ENABLE)
            self.set_atr_txval(     0)
            self.set_atr_rxval(ENABLE)
        else:
            self.set_atr_mask (0)
            self.set_atr_txval(0)
            self.set_atr_rxval(0)

    def select_rx_antenna(self, which_antenna):