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📄 me.fit.rpt

📁 曼彻斯特编解码 用vhdl编写的
💻 RPT
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Fitter report for me
Wed May 07 14:01:52 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Failed - Wed May 07 14:01:52 2008        ;
; Quartus II Version    ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name         ; me                                       ;
; Top-level Entity Name ; me                                       ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C3T100C8                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 38                                       ;
; Total pins            ; 13                                       ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0                                        ;
; Total PLLs            ; 0                                        ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP1C3T100C8                    ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                   ; Care                           ; Care                           ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+---------------------------------------------------------------+
; Fitter Device Options                                         ;
+----------------------------------------------+----------------+
; Option                                       ; Setting        ;
+----------------------------------------------+----------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off            ;
; Enable device-wide reset (DEV_CLRn)          ; Off            ;
; Enable device-wide output enable (DEV_OE)    ; Off            ;
; Enable INIT_DONE output                      ; Off            ;
; Configuration scheme                         ; Passive Serial ;
; Error detection CRC                          ; Off            ;
; ASDO,nCSO                                    ; Unreserved     ;
; Reserve all unused pins                      ; Unreserved     ;
; Base pin-out file on sameframe device        ; Off            ;
+----------------------------------------------+----------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed May 07 14:01:51 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off me -c me
Warning: FLEXlm software error: Invalid (inconsistent) license key  The license-key and data for the feature do not match.  This usually happens when a license file has been altered Feature:       quartus License path:  D:\programe\Crack_QII72\Crack_QII72\license.DAT FLEXlm error:  -8,523 For further information, refer to the FLEXlm End User Manual, available at "www.macrovision.com".
Error: Current license file does not support the EP1C3T100C8 device
Error: Quartus II Fitter was unsuccessful. 1 error, 1 warning
    Info: Allocated 131 megabytes of memory during processing
    Error: Processing ended: Wed May 07 14:01:52 2008
    Error: Elapsed time: 00:00:01


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