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; SMIC 0.18um Logic/Mixed-Signal/RF Salicide (1P6M, Thick Top Metal, 1.8V/3.3V) process<chip> chipx = 1024 ; dimensions of the chip in x direction chipy = 1024 ; dimensions of the chip in y direction fftx = 256 ; x-fft size (must be a power of 2) ffty = 256 ; y-fft size TechFile = smic018.tek ; name of this file! TechPath = ./ ; pathname where you stored the files ; which is generated by gendata freq = 1.5 ; GHz eddy = 0 eddy = 1 <layer> 0 ; substrate/nwell rho = 8 ; resistivity (ohm-cm) t = 250 ; thickness (microns) eps = 11.9 ; Permitivity: relative<layer> 1 ; FOX layer rho = 1e10 ; resistivity (ohm-cm) t = 0.354 ; thickness (microns) eps = 4.0<layer> 2 ; ILD Layer (ILD1a + ILD1b) rho = 1e10 ; resistivity, insulator in this case t = 0.79 ; thickness eps = 4.2<layer> 3 ; IMD1a Layer rho = 1e10 ; resistivity,insulator in this case t = 1.18 ; thickness eps = 3.7<layer> 4 ; IMD1b Layer rho = 1e10 ; resistivity,insulator in this case t = 0.2 ; thickness eps = 4.2<layer> 5 ; IMD2a Layer rho = 1e10 ; resistivity,insulator in this case t = 1.18 ; thickness eps = 3.7<layer> 6 ; IMD2b Layer rho = 1e10 ; resistivity,insulator in this case t = 0.2 ; thickness eps = 4.2<layer> 7 ; IMD3a Layer rho = 1e10 ; resistivity,insulator in this case t = 1.18 ; thickness eps = 3.7<layer> 8 ; IMD3b Layer rho = 1e10 ; resistivity,insulator in this case t = 0.2 ; thickness eps = 4.2<layer> 9 ; IMD4a Layer rho = 1e10 ; resistivity,insulator in this case t = 1.18 ; thickness eps = 3.7<layer> 10 ; IMD4b Layer rho = 1e10 ; resistivity,insulator in this case t = 0.2 ; thickness eps = 4.2<layer> 11 ; IMD5a Layer rho = 1e10 ; resistivity,insulator in this case t = 1.18 ; thickness eps = 3.7<layer> 12 ; IMD5b Layer rho = 1e10 ; resistivity,insulator in this case t = 0.35 ; thickness eps = 4.2<layer> 13 ; PASS1 Layer rho = 1e10 ; resistivity,insulator in this case t = 4.67 ; thickness eps = 4.2<layer> 14 ; PASS3 Layer rho = 1e10 ; resistivity,insulator in this case t = 0.6 ; thickness eps = 7.9 <layer> 15 ; Air Layer rho = 1e10 ; resistivity,insulator in this case t = 10.0 ; thickness eps = 1.0 <metal> 0 ; substrate tap layer = 2 ; what layer is the metal in? rsh = 8180.0 ; sheet resistance Milli-ohms/Square t = 0.2 ; thickness of metal d = 0.0 ; distance from bottom of layer name = mpoly ; name to use inside asitic color = green ; color in asitic <via> 0 ; metal 1 to substrate top = 1 ; via connects up to this metal layer bottom = 0 ; via connects down to this metal layer r = 15 ; resistance per via width = 0.22 ; width of via space = 0.25 ; minimum spacing between vias overplot1 = 0.1 ; minimum dist to substrate metal overplot2 = 0.06 ; minimum dist to metal 1 name = via0 ; name in ASITIC color = purple ; color in ASITIC<metal> 1 layer = 3 rsh = 78 t = 0.53 d = 0.0 name = m1 color = blue <via> 1 ; metal 1 to metal 2 top = 2 bottom = 1 r = 4 width = 0.26 space = 0.26 overplot1 = 0.06 ; to substrate metal overplot2 = 0.06 ; to metal 1 name = via1 color = white<metal> 2 layer = 5 rsh = 78 t = 0.53 d = 0.0 name = m2 color = red<via> 2 ; metal 2 to metal 3 top = 3 bottom = 2 r = 4 width = 0.26 space = 0.26 overplot1 = 0.06 ; to substrate metal overplot2 = 0.06 ; to metal 1 name = via2 color = green<metal> 3 layer = 7 rsh = 78 t = 0.53 d = 0.0 name = m3 color = light yellow<via> 3 ; metal 3 to metal 4 top = 4 bottom = 3 r = 4 width = 0.26 space = 0.26 overplot1 = 0.06 overplot2 = 0.06 name = via3 color = red <metal> 4 layer = 9 rsh = 78 t = 0.53 d = 0.0 name = m4 color = light red <via> 4 ; metal 4 to metal 5 top = 5 bottom = 4 r = 4 width = 0.26 space = 0.26 overplot1 = 0.06 overplot2 = 0.06 name = via4 color = grey <metal> 5 layer = 11 rsh = 78 t = 0.53 d = 0.0 name = m5 color = light blue <via> 5 ; metal 5 to metal 6 top = 6 bottom = 5 r = 2 width = 0.36 space = 0.35 overplot1 = 0.06 overplot2 = 0.42 name = via5 color = yellow<metal> 6 layer = 13 rsh = 19 t = 2.17 d = 0.0 name = m6 color = light green
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