📄 controller.tan.rpt
字号:
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; CLR ; COUNTER[2] ; CLK ; CLK ; None ; None ; 0.967 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; CLR ; COUNTER[1] ; CLK ; CLK ; None ; None ; 0.932 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s0 ; STATE.s1 ; CLK ; CLK ; None ; None ; 0.920 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s2 ; LIGHTB[0] ; CLK ; CLK ; None ; None ; 0.902 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; CLR ; COUNTER[0] ; CLK ; CLK ; None ; None ; 0.878 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s1 ; CLR ; CLK ; CLK ; None ; None ; 0.821 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s1 ; STATE.s2 ; CLK ; CLK ; None ; None ; 0.804 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s2 ; CLR ; CLK ; CLK ; None ; None ; 0.789 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[0] ; COUNTER[4] ; CLK ; CLK ; None ; None ; 0.785 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s2 ; STATE.s3 ; CLK ; CLK ; None ; None ; 0.780 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s3 ; STATE.s0 ; CLK ; CLK ; None ; None ; 0.776 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[1] ; COUNTER[4] ; CLK ; CLK ; None ; None ; 0.750 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[0] ; COUNTER[3] ; CLK ; CLK ; None ; None ; 0.750 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[2] ; COUNTER[4] ; CLK ; CLK ; None ; None ; 0.715 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[1] ; COUNTER[3] ; CLK ; CLK ; None ; None ; 0.715 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[0] ; COUNTER[2] ; CLK ; CLK ; None ; None ; 0.715 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s0 ; CLR ; CLK ; CLK ; None ; None ; 0.704 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s3 ; CLR ; CLK ; CLK ; None ; None ; 0.692 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[3] ; COUNTER[4] ; CLK ; CLK ; None ; None ; 0.680 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[2] ; COUNTER[3] ; CLK ; CLK ; None ; None ; 0.680 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[1] ; COUNTER[2] ; CLK ; CLK ; None ; None ; 0.680 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[0] ; COUNTER[1] ; CLK ; CLK ; None ; None ; 0.680 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s0 ; LIGHTA[2] ; CLK ; CLK ; None ; None ; 0.628 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s0 ; LIGHTA[0] ; CLK ; CLK ; None ; None ; 0.628 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s3 ; LIGHTB[1] ; CLK ; CLK ; None ; None ; 0.619 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[0] ; COUNTER[0] ; CLK ; CLK ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[4] ; COUNTER[4] ; CLK ; CLK ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[3] ; COUNTER[3] ; CLK ; CLK ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[2] ; COUNTER[2] ; CLK ; CLK ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[1] ; COUNTER[1] ; CLK ; CLK ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s1 ; LIGHTA[1] ; CLK ; CLK ; None ; None ; 0.507 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s1 ; STATE.s1 ; CLK ; CLK ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s2 ; STATE.s2 ; CLK ; CLK ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s0 ; STATE.s0 ; CLK ; CLK ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s3 ; STATE.s3 ; CLK ; CLK ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; STATE.s1 ; LIGHTA[2] ; CLK ; CLK ; None ; None ; 0.436 ns ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------+----+------------+
; N/A ; None ; 6.368 ns ; LIGHTA[2] ; RB ; CLK ;
; N/A ; None ; 6.368 ns ; LIGHTA[2] ; RA ; CLK ;
; N/A ; None ; 6.307 ns ; LIGHTA[1] ; YA ; CLK ;
; N/A ; None ; 6.058 ns ; LIGHTB[0] ; GB ; CLK ;
; N/A ; None ; 5.799 ns ; LIGHTA[0] ; GA ; CLK ;
; N/A ; None ; 5.739 ns ; LIGHTB[1] ; YB ; CLK ;
+-------+--------------+------------+-----------+----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Thu Nov 06 10:37:59 2008
Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off CONTROLLER -c CONTROLLER
Info: Started post-fitting delay annotation
Warning: Found 6 output pins without output pin load capacitance assignment
Info: Pin "RA" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "YA" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "GA" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "RB" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "YB" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "GB" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 386.25 MHz between source register "CLR" and destination register "STATE.s2" (period= 2.589 ns)
Info: + Longest register to register delay is 2.405 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y10_N29; Fanout = 10; REG Node = 'CLR'
Info: 2: + IC(0.401 ns) + CELL(0.309 ns) = 0.710 ns; Loc. = LCCOMB_X26_Y10_N0; Fanout = 2; COMB Node = 'Add0~77'
Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.745 ns; Loc. = LCCOMB_X26_Y10_N2; Fanout = 2; COMB Node = 'Add0~81'
Info: 4: + IC(0.000 ns) + CELL(0.125 ns) = 0.870 ns; Loc. = LCCOMB_X26_Y10_N4; Fanout = 2; COMB Node = 'Add0~84'
Info: 5: + IC(0.298 ns) + CELL(0.228 ns) = 1.396 ns; Loc. = LCCOMB_X26_Y10_N14; Fanout = 2; COMB Node = 'Equal0~64'
Info: 6: + IC(0.218 ns) + CELL(0.053 ns) = 1.667 ns; Loc. = LCCOMB_X26_Y10_N26; Fanout = 5; COMB Node = 'Equal1~30'
Info: 7: + IC(0.355 ns) + CELL(0.228 ns) = 2.250 ns; Loc. = LCCOMB_X26_Y10_N18; Fanout = 1; COMB Node = 'Selector2~68'
Info: 8: + IC(0.000 ns) + CELL(0.155 ns) = 2.405 ns; Loc. = LCFF_X26_Y10_N19; Fanout = 4; REG Node = 'STATE.s2'
Info: Total cell delay = 1.133 ns ( 47.11 % )
Info: Total interconnect delay = 1.272 ns ( 52.89 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLK" to destination register is 2.486 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(0.671 ns) + CELL(0.618 ns) = 2.486 ns; Loc. = LCFF_X26_Y10_N19; Fanout = 4; REG Node = 'STATE.s2'
Info: Total cell delay = 1.472 ns ( 59.21 % )
Info: Total interconnect delay = 1.014 ns ( 40.79 % )
Info: - Longest clock path from clock "CLK" to source register is 2.486 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(0.671 ns) + CELL(0.618 ns) = 2.486 ns; Loc. = LCFF_X26_Y10_N29; Fanout = 10; REG Node = 'CLR'
Info: Total cell delay = 1.472 ns ( 59.21 % )
Info: Total interconnect delay = 1.014 ns ( 40.79 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Info: tco from clock "CLK" to destination pin "RB" through register "LIGHTA[2]" is 6.368 ns
Info: + Longest clock path from clock "CLK" to source register is 2.486 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(0.671 ns) + CELL(0.618 ns) = 2.486 ns; Loc. = LCFF_X26_Y10_N21; Fanout = 2; REG Node = 'LIGHTA[2]'
Info: Total cell delay = 1.472 ns ( 59.21 % )
Info: Total interconnect delay = 1.014 ns ( 40.79 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Longest register to pin delay is 3.788 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y10_N21; Fanout = 2; REG Node = 'LIGHTA[2]'
Info: 2: + IC(1.742 ns) + CELL(2.046 ns) = 3.788 ns; Loc. = PIN_B9; Fanout = 0; PIN Node = 'RB'
Info: Total cell delay = 2.046 ns ( 54.01 % )
Info: Total interconnect delay = 1.742 ns ( 45.99 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
Info: Allocated 132 megabytes of memory during processing
Info: Processing ended: Thu Nov 06 10:38:01 2008
Info: Elapsed time: 00:00:02
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