📄 controller.tan.rpt
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Classic Timing Analyzer report for CONTROLLER
Thu Nov 06 10:38:00 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------+----------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 6.368 ns ; LIGHTA[2] ; RA ; CLK ; -- ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; 386.25 MHz ( period = 2.589 ns ) ; CLR ; STATE.s2 ; CLK ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-----------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2S15F484C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 386.25 MHz ( period = 2.589 ns ) ; CLR ; STATE.s2 ; CLK ; CLK ; None ; None ; 2.405 ns ;
; N/A ; 400.80 MHz ( period = 2.495 ns ) ; CLR ; STATE.s0 ; CLK ; CLK ; None ; None ; 2.311 ns ;
; N/A ; 401.28 MHz ( period = 2.492 ns ) ; CLR ; STATE.s1 ; CLK ; CLK ; None ; None ; 2.308 ns ;
; N/A ; 402.74 MHz ( period = 2.483 ns ) ; CLR ; STATE.s3 ; CLK ; CLK ; None ; None ; 2.299 ns ;
; N/A ; 403.06 MHz ( period = 2.481 ns ) ; CLR ; CLR ; CLK ; CLK ; None ; None ; 2.297 ns ;
; N/A ; 427.90 MHz ( period = 2.337 ns ) ; COUNTER[0] ; STATE.s2 ; CLK ; CLK ; None ; None ; 2.153 ns ;
; N/A ; 434.40 MHz ( period = 2.302 ns ) ; COUNTER[1] ; STATE.s2 ; CLK ; CLK ; None ; None ; 2.118 ns ;
; N/A ; 445.83 MHz ( period = 2.243 ns ) ; COUNTER[0] ; STATE.s0 ; CLK ; CLK ; None ; None ; 2.059 ns ;
; N/A ; 446.43 MHz ( period = 2.240 ns ) ; COUNTER[0] ; STATE.s1 ; CLK ; CLK ; None ; None ; 2.056 ns ;
; N/A ; 448.23 MHz ( period = 2.231 ns ) ; COUNTER[2] ; STATE.s2 ; CLK ; CLK ; None ; None ; 2.047 ns ;
; N/A ; 448.23 MHz ( period = 2.231 ns ) ; COUNTER[0] ; STATE.s3 ; CLK ; CLK ; None ; None ; 2.047 ns ;
; N/A ; 448.63 MHz ( period = 2.229 ns ) ; COUNTER[0] ; CLR ; CLK ; CLK ; None ; None ; 2.045 ns ;
; N/A ; 452.90 MHz ( period = 2.208 ns ) ; COUNTER[1] ; STATE.s0 ; CLK ; CLK ; None ; None ; 2.024 ns ;
; N/A ; 453.51 MHz ( period = 2.205 ns ) ; COUNTER[1] ; STATE.s1 ; CLK ; CLK ; None ; None ; 2.021 ns ;
; N/A ; 455.37 MHz ( period = 2.196 ns ) ; COUNTER[1] ; STATE.s3 ; CLK ; CLK ; None ; None ; 2.012 ns ;
; N/A ; 455.79 MHz ( period = 2.194 ns ) ; COUNTER[1] ; CLR ; CLK ; CLK ; None ; None ; 2.010 ns ;
; N/A ; 467.95 MHz ( period = 2.137 ns ) ; COUNTER[2] ; STATE.s0 ; CLK ; CLK ; None ; None ; 1.953 ns ;
; N/A ; 468.60 MHz ( period = 2.134 ns ) ; COUNTER[2] ; STATE.s1 ; CLK ; CLK ; None ; None ; 1.950 ns ;
; N/A ; 470.59 MHz ( period = 2.125 ns ) ; COUNTER[2] ; STATE.s3 ; CLK ; CLK ; None ; None ; 1.941 ns ;
; N/A ; 471.03 MHz ( period = 2.123 ns ) ; COUNTER[2] ; CLR ; CLK ; CLK ; None ; None ; 1.939 ns ;
; N/A ; 476.42 MHz ( period = 2.099 ns ) ; COUNTER[3] ; STATE.s2 ; CLK ; CLK ; None ; None ; 1.915 ns ;
; N/A ; 493.10 MHz ( period = 2.028 ns ) ; COUNTER[4] ; STATE.s2 ; CLK ; CLK ; None ; None ; 1.844 ns ;
; N/A ; 498.75 MHz ( period = 2.005 ns ) ; COUNTER[3] ; STATE.s0 ; CLK ; CLK ; None ; None ; 1.821 ns ;
; N/A ; 499.50 MHz ( period = 2.002 ns ) ; COUNTER[3] ; STATE.s1 ; CLK ; CLK ; None ; None ; 1.818 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[3] ; CLR ; CLK ; CLK ; None ; None ; 1.807 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[4] ; STATE.s0 ; CLK ; CLK ; None ; None ; 1.750 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[4] ; STATE.s1 ; CLK ; CLK ; None ; None ; 1.747 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[4] ; CLR ; CLK ; CLK ; None ; None ; 1.736 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[3] ; STATE.s3 ; CLK ; CLK ; None ; None ; 1.727 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; COUNTER[4] ; STATE.s3 ; CLK ; CLK ; None ; None ; 1.656 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; CLR ; COUNTER[4] ; CLK ; CLK ; None ; None ; 1.037 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; CLR ; COUNTER[3] ; CLK ; CLK ; None ; None ; 1.002 ns ;
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