controller.map.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 06 10:37:29 2008 " "Info: Processing started: Thu Nov 06 10:37:29 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CONTROLLER -c CONTROLLER " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CONTROLLER -c CONTROLLER" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CONTROLLER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CONTROLLER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CONTROLLER-ONE " "Info: Found design unit 1: CONTROLLER-ONE" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CONTROLLER " "Info: Found entity 1: CONTROLLER" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CONTROLLER " "Info: Elaborating entity \"CONTROLLER\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "CNT CLR " "Info: Duplicate register \"CNT\" merged to single register \"CLR\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 21 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "LIGHTB\[2\] LIGHTA\[2\] " "Info: Duplicate register \"LIGHTB\[2\]\" merged to single register \"LIGHTA\[2\]\", power-up level changed" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 23 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|CONTROLLER\|STATE 4 " "Info: State machine \"\|CONTROLLER\|STATE\" contains 4 states" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|CONTROLLER\|STATE " "Info: Selected Auto state machine encoding method for state machine \"\|CONTROLLER\|STATE\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|CONTROLLER\|STATE " "Info: Encoding result for state machine \"\|CONTROLLER\|STATE\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.s3 " "Info: Encoded state bit \"STATE.s3\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.s2 " "Info: Encoded state bit \"STATE.s2\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.s1 " "Info: Encoded state bit \"STATE.s1\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.s0 " "Info: Encoded state bit \"STATE.s0\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CONTROLLER\|STATE.s0 0000 " "Info: State \"\|CONTROLLER\|STATE.s0\" uses code string \"0000\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CONTROLLER\|STATE.s1 0011 " "Info: State \"\|CONTROLLER\|STATE.s1\" uses code string \"0011\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CONTROLLER\|STATE.s2 0101 " "Info: State \"\|CONTROLLER\|STATE.s2\" uses code string \"0101\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CONTROLLER\|STATE.s3 1001 " "Info: State \"\|CONTROLLER\|STATE.s3\" uses code string \"1001\"" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "30 " "Info: Implemented 30 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "23 " "Info: Implemented 23 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "147 " "Info: Allocated 147 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 06 10:37:32 2008 " "Info: Processing ended: Thu Nov 06 10:37:32 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}