controller.tan.qmsg

NEW！！ 交通灯实验报告 全面

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CLR register STATE.s2 386.25 MHz 2.589 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 386.25 MHz between source register \"CLR\" and destination register \"STATE.s2\" (period= 2.589 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.405 ns + Longest register register " "Info: + Longest register to register delay is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLR 1 REG LCFF_X26_Y10_N29 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y10_N29; Fanout = 10; REG Node = 'CLR'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.309 ns) 0.710 ns Add0~77 2 COMB LCCOMB_X26_Y10_N0 2 " "Info: 2: + IC(0.401 ns) + CELL(0.309 ns) = 0.710 ns; Loc. = LCCOMB_X26_Y10_N0; Fanout = 2; COMB Node = 'Add0~77'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.710 ns" { CLR Add0~77 } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.745 ns Add0~81 3 COMB LCCOMB_X26_Y10_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.745 ns; Loc. = LCCOMB_X26_Y10_N2; Fanout = 2; COMB Node = 'Add0~81'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~77 Add0~81 } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 0.870 ns Add0~84 4 COMB LCCOMB_X26_Y10_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.125 ns) = 0.870 ns; Loc. = LCCOMB_X26_Y10_N4; Fanout = 2; COMB Node = 'Add0~84'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { Add0~81 Add0~84 } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.298 ns) + CELL(0.228 ns) 1.396 ns Equal0~64 5 COMB LCCOMB_X26_Y10_N14 2 " "Info: 5: + IC(0.298 ns) + CELL(0.228 ns) = 1.396 ns; Loc. = LCCOMB_X26_Y10_N14; Fanout = 2; COMB Node = 'Equal0~64'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.526 ns" { Add0~84 Equal0~64 } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.218 ns) + CELL(0.053 ns) 1.667 ns Equal1~30 6 COMB LCCOMB_X26_Y10_N26 5 " "Info: 6: + IC(0.218 ns) + CELL(0.053 ns) = 1.667 ns; Loc. = LCCOMB_X26_Y10_N26; Fanout = 5; COMB Node = 'Equal1~30'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.271 ns" { Equal0~64 Equal1~30 } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.355 ns) + CELL(0.228 ns) 2.250 ns Selector2~68 7 COMB LCCOMB_X26_Y10_N18 1 " "Info: 7: + IC(0.355 ns) + CELL(0.228 ns) = 2.250 ns; Loc. = LCCOMB_X26_Y10_N18; Fanout = 1; COMB Node = 'Selector2~68'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.583 ns" { Equal1~30 Selector2~68 } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.405 ns STATE.s2 8 REG LCFF_X26_Y10_N19 4 " "Info: 8: + IC(0.000 ns) + CELL(0.155 ns) = 2.405 ns; Loc. = LCFF_X26_Y10_N19; Fanout = 4; REG Node = 'STATE.s2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Selector2~68 STATE.s2 } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.133 ns ( 47.11 % ) " "Info: Total cell delay = 1.133 ns ( 47.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.272 ns ( 52.89 % ) " "Info: Total interconnect delay = 1.272 ns ( 52.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.405 ns" { CLR Add0~77 Add0~81 Add0~84 Equal0~64 Equal1~30 Selector2~68 STATE.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.405 ns" { CLR Add0~77 Add0~81 Add0~84 Equal0~64 Equal1~30 Selector2~68 STATE.s2 } { 0.000ns 0.401ns 0.000ns 0.000ns 0.298ns 0.218ns 0.355ns 0.000ns } { 0.000ns 0.309ns 0.035ns 0.125ns 0.228ns 0.053ns 0.228ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.486 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.486 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 15 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.618 ns) 2.486 ns STATE.s2 3 REG LCFF_X26_Y10_N19 4 " "Info: 3: + IC(0.671 ns) + CELL(0.618 ns) = 2.486 ns; Loc. = LCFF_X26_Y10_N19; Fanout = 4; REG Node = 'STATE.s2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.289 ns" { CLK~clkctrl STATE.s2 } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.21 % ) " "Info: Total cell delay = 1.472 ns ( 59.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.014 ns ( 40.79 % ) " "Info: Total interconnect delay = 1.014 ns ( 40.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { CLK CLK~clkctrl STATE.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.486 ns" { CLK CLK~combout CLK~clkctrl STATE.s2 } { 0.000ns 0.000ns 0.343ns 0.671ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.486 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.486 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 15 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.618 ns) 2.486 ns CLR 3 REG LCFF_X26_Y10_N29 10 " "Info: 3: + IC(0.671 ns) + CELL(0.618 ns) = 2.486 ns; Loc. = LCFF_X26_Y10_N29; Fanout = 10; REG Node = 'CLR'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.289 ns" { CLK~clkctrl CLR } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.21 % ) " "Info: Total cell delay = 1.472 ns ( 59.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.014 ns ( 40.79 % ) " "Info: Total interconnect delay = 1.014 ns ( 40.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { CLK CLK~clkctrl CLR } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.486 ns" { CLK CLK~combout CLK~clkctrl CLR } { 0.000ns 0.000ns 0.343ns 0.671ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { CLK CLK~clkctrl STATE.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.486 ns" { CLK CLK~combout CLK~clkctrl STATE.s2 } { 0.000ns 0.000ns 0.343ns 0.671ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { CLK CLK~clkctrl CLR } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.486 ns" { CLK CLK~combout CLK~clkctrl CLR } { 0.000ns 0.000ns 0.343ns 0.671ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.405 ns" { CLR Add0~77 Add0~81 Add0~84 Equal0~64 Equal1~30 Selector2~68 STATE.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.405 ns" { CLR Add0~77 Add0~81 Add0~84 Equal0~64 Equal1~30 Selector2~68 STATE.s2 } { 0.000ns 0.401ns 0.000ns 0.000ns 0.298ns 0.218ns 0.355ns 0.000ns } { 0.000ns 0.309ns 0.035ns 0.125ns 0.228ns 0.053ns 0.228ns 0.155ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { CLK CLK~clkctrl STATE.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.486 ns" { CLK CLK~combout CLK~clkctrl STATE.s2 } { 0.000ns 0.000ns 0.343ns 0.671ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { CLK CLK~clkctrl CLR } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.486 ns" { CLK CLK~combout CLK~clkctrl CLR } { 0.000ns 0.000ns 0.343ns 0.671ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK RB LIGHTA\[2\] 6.368 ns register " "Info: tco from clock \"CLK\" to destination pin \"RB\" through register \"LIGHTA\[2\]\" is 6.368 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.486 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.486 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 15 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.618 ns) 2.486 ns LIGHTA\[2\] 3 REG LCFF_X26_Y10_N21 2 " "Info: 3: + IC(0.671 ns) + CELL(0.618 ns) = 2.486 ns; Loc. = LCFF_X26_Y10_N21; Fanout = 2; REG Node = 'LIGHTA\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.289 ns" { CLK~clkctrl LIGHTA[2] } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.21 % ) " "Info: Total cell delay = 1.472 ns ( 59.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.014 ns ( 40.79 % ) " "Info: Total interconnect delay = 1.014 ns ( 40.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { CLK CLK~clkctrl LIGHTA[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.486 ns" { CLK CLK~combout CLK~clkctrl LIGHTA[2] } { 0.000ns 0.000ns 0.343ns 0.671ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.788 ns + Longest register pin " "Info: + Longest register to pin delay is 3.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LIGHTA\[2\] 1 REG LCFF_X26_Y10_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y10_N21; Fanout = 2; REG Node = 'LIGHTA\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LIGHTA[2] } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.742 ns) + CELL(2.046 ns) 3.788 ns RB 2 PIN PIN_B9 0 " "Info: 2: + IC(1.742 ns) + CELL(2.046 ns) = 3.788 ns; Loc. = PIN_B9; Fanout = 0; PIN Node = 'RB'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.788 ns" { LIGHTA[2] RB } "NODE_NAME" } } { "CONTROLLER.vhd" "" { Text "F:/CONTROLLER/CONTROLLER.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.046 ns ( 54.01 % ) " "Info: Total cell delay = 2.046 ns ( 54.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.742 ns ( 45.99 % ) " "Info: Total interconnect delay = 1.742 ns ( 45.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.788 ns" { LIGHTA[2] RB } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.788 ns" { LIGHTA[2] RB } { 0.000ns 1.742ns } { 0.000ns 2.046ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { CLK CLK~clkctrl LIGHTA[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.486 ns" { CLK CLK~combout CLK~clkctrl LIGHTA[2] } { 0.000ns 0.000ns 0.343ns 0.671ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.788 ns" { LIGHTA[2] RB } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.788 ns" { LIGHTA[2] RB } { 0.000ns 1.742ns } { 0.000ns 2.046ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "132 " "Info: Allocated 132 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 06 10:38:01 2008 " "Info: Processing ended: Thu Nov 06 10:38:01 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}