📄 controller.vhd.bak
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CONTROLLER IS
PORT(CLK:IN STD_LOGIC;
RA,YA,GA,RB,YB,GB:OUT STD_LOGIC);
END CONTROLLER;
ARCHITECTURE ONE OF CONTROLLER IS
TYPE STATES IS(S0,S1,S2,S3);
SIGNAL STATE : STATES;
SIGNAL LIGHTA : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL LIGHTB : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
RA<=LIGHTA(2);
YA<=LIGHTA(1);
GA<=LIGHTA(0);
RB<=LIGHTB(2);
YB<=LIGHTB(1);
GB<=LIGHTB(0);
PROCESS(CLK)
VARIABLE COUNTER: INTEGER RANGE 0 TO 29;
VARIABLE CLR,CNT:STD_LOGIC;
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF CLR='0' THEN
COUNTER :=0;
ELSIF CNT='0' THEN
COUNTER:=COUNTER;
ELSE COUNTER:=COUNTER+1;
END IF;
CASE STATE IS
WHEN S0=>LIGHTA<="001";
LIGHTB<="100";
IF COUNTER=29 THEN
STATE<=S1;
CLR:='0';
CNT:='0';
ELSE
CLR:='1';
CNT:='1';
STATE<=S0;
END IF;
WHEN S1=>LIGHTA<="010";
LIGHTB<="010";
IF COUNTER=4 THEN
STATE<=S2;
CLR:='0';
CNT:='0';
ELSE
STATE<=S1;
CLR:='1';
CNT:='1';
END IF;
WHEN S2=>LIGHTA<="100";
LIGHTB<="001";
IF COUNTER=29 THEN
STATE <=S3;
CLR:='0';
CNT:='0';
ELSE
STATE<=S2;
CLR:='1';
CNT:='1';
END IF;
WHEN S3=>LIGHTA<="010";
LIGHTB<="010";
IF COUNTER=4 THEN
STATE<=S0;
CLR:='0';
CNT:='0';
ELSE
STATE<=S3;
CLR:='1';
CNT:='1';
END IF;
END CASE;
END IF;
END PROCESS;
END ONE;
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