controller.map.rpt

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+----------------------------------+-----------------+-----------------+------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 15    ;
; Dedicated logic registers                     ; 15    ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 2     ;
;                                               ;       ;
; Total combinational functions                 ; 15    ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 0     ;
;     -- 6 input functions                      ; 1     ;
;     -- 5 input functions                      ; 2     ;
;     -- 4 input functions                      ; 4     ;
;     -- <=3 input functions                    ; 8     ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 10    ;
;     -- extended LUT mode                      ; 0     ;
;     -- arithmetic mode                        ; 5     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 17    ;
;                                               ;       ;
; Total registers                               ; 15    ;
;     -- Dedicated logic registers              ; 15    ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 9     ;
;                                               ;       ;
; I/O pins                                      ; 7     ;
; Maximum fan-out node                          ; CLK   ;
; Maximum fan-out                               ; 15    ;
; Total fan-out                                 ; 89    ;
; Average fan-out                               ; 2.41  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |CONTROLLER                ; 15 (15)           ; 15 (15)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 7    ; 0            ; |CONTROLLER         ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+------------------------------------------------------+
; State Machine - |CONTROLLER|STATE                    ;
+----------+----------+----------+----------+----------+
; Name     ; STATE.s3 ; STATE.s2 ; STATE.s1 ; STATE.s0 ;
+----------+----------+----------+----------+----------+
; STATE.s0 ; 0        ; 0        ; 0        ; 0        ;
; STATE.s1 ; 0        ; 0        ; 1        ; 1        ;
; STATE.s2 ; 0        ; 1        ; 0        ; 1        ;
; STATE.s3 ; 1        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+


+---------------------------------------------------------------+
; Registers Removed During Synthesis                            ;
+---------------------------------------+-----------------------+
; Register name                         ; Reason for Removal    ;
+---------------------------------------+-----------------------+
; CNT                                   ; Merged with CLR       ;
; LIGHTB[2]                             ; Merged with LIGHTA[2] ;
; Total Number of Removed Registers = 2 ;                       ;
+---------------------------------------+-----------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 15    ;
; Number of registers using Synchronous Clear  ; 5     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Nov 06 10:37:29 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CONTROLLER -c CONTROLLER
Info: Found 2 design units, including 1 entities, in source file CONTROLLER.vhd
    Info: Found design unit 1: CONTROLLER-ONE
    Info: Found entity 1: CONTROLLER
Info: Elaborating entity "CONTROLLER" for the top level hierarchy
Info: Duplicate registers merged to single register
    Info: Duplicate register "CNT" merged to single register "CLR"
    Info: Duplicate register "LIGHTB[2]" merged to single register "LIGHTA[2]", power-up level changed
Info: State machine "|CONTROLLER|STATE" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|CONTROLLER|STATE"
Info: Encoding result for state machine "|CONTROLLER|STATE"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "STATE.s3"
        Info: Encoded state bit "STATE.s2"
        Info: Encoded state bit "STATE.s1"
        Info: Encoded state bit "STATE.s0"
    Info: State "|CONTROLLER|STATE.s0" uses code string "0000"
    Info: State "|CONTROLLER|STATE.s1" uses code string "0011"
    Info: State "|CONTROLLER|STATE.s2" uses code string "0101"
    Info: State "|CONTROLLER|STATE.s3" uses code string "1001"
Info: Implemented 30 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 6 output pins
    Info: Implemented 23 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 147 megabytes of memory during processing
    Info: Processing ended: Thu Nov 06 10:37:32 2008
    Info: Elapsed time: 00:00:03