c5402dsk.cmd

该代码用于定义TI公司C54x系列DSP的内存资源的分配

/*************************************************************************
* $RCSFile: /db/sds/syseng/rtdx/target/examples/54x/c5402.cmd,v $
* $Revision: 1.1 $
* $Date: 2000/09/20 16:48:39 $
* Copyright (c) 2000 Texas Instruments Incorporated
*
* LINKER COMMAND FILE FOR TMS5402 DSK Target
*
*   Usage:  lnk500 <obj files...>    -o <out file> -m <map file> c5402.cmd
*           cl500  <src files...> -z -o <out file> -m <map file> c5402.cmd
*
*   Description: This file is a sample command file that can be used
*                for linking programs built with the TMS54x C Compiler.   
*                Use it as a guideline; you may want to change
*                the allocation scheme according to the size of your
*                program and the memory layout of your target system.
*************************************************************************/
-c /* copy constants in .cinit to global variables at boot time */
-stack 0x0400
-heap  0x0400

/* This symbol defines the interrupt mask to be applied to IMR inside
   RTDX Critical Code sections.

   This example masks the timer interrupt.
*/
_RTDX_interrupt_mask = ~0x0008; /* interrupts masked by RTDX */


/* Note: The default power-up state of board is PMST = 0xffa0, but we
    set it to 0xffe0 in a GEL file.

                            PMST Values
    PMST Bit    Name    0xffe0  0xffa0  0xffc0
    ========    ====    =====   ======  ======
    15-7        IPTR    0x1ff   0x1ff   0x1ff
    6           MP/!MC  1       0       1
    5           OVLY    1       1       0
    3           DROM    0       0       0

Note: Memory between 0x0080-0x8000 is shared if OVLY = 1.

Note: PMEM0/DMEM0 will be flash memory if FLASHENB = 1.  
This memory may be recovered as SRAM by setting to 0.
*/


MEMORY  
{

    PAGE 0: /* Program Space */
        RSV0    (R  ) : o=000000h l=000080h 	/* Reserved            	ovly=1 	*/
        RSV0    (R  ) : o=000000h l=000080h 	/* External RAM Page 0 	ovly=0  */
        DARAM1  (RWX) : o=000080h l=003f80h 	/* On-Chip DARAM       	ovly=1 	*/
        DARAM1  (RWX) : o=000080h l=003f80h 	/* External RAM Page 0 	ovly=0 	*/
        PMEM0   (RWX) : o=004000h l=00bf80h 	/* External RAM Page 0 	mp/mc=1 */
        PMEM0   (RWX) : o=004000h l=00b000h 	/* Reserved				mp/mc=0 */
        ROM     (RX ) : o=00f000h l=000f00h 	/* On-Chip ROM         	mp/mc=0 */
        RSV1    (R  ) : o=00ff00h l=000080h 	/* Reserved             mp/mc=0 */
        VECS    (RWX) : o=00ff80h l=000080h 	/* Interrupt Vector Table mp/mc=0*/
    

    PAGE 1: /* Data Space */
        MMRS    (RW ) : o=000000h l=000060h 	/* Memory-mapped registers  */
        SCRATCH (RW ) : o=000060h l=000020h 	/* scratch-pad DARAM        */

        /* declaration for DARAM already made in PAGE 0                 */
        DARAM2  (RW ) : o=000080h l=003f80h  	/*On-Chip DARAM              */
        DMEM0   (RW ) : o=004000h l=00c000h  	/* External Data RAM   DROM=0    */
        DMEM0   (RW ) : o=004000h l=00b000h  	/* External Data RAM   DROM=1    */
        DMEM1   (RW ) : o=00f000h l=000f00h  	/* On-Chip ROM         DROM=1    */
        DMEM2   (RW ) : o=00ff00h l=000100h  	/* Reserved            DROM=1    */
        
    PAGE 2: /* I/O Space */
        CPLD    (RW ) : o=000000h l=004000h 	/* CPLD Control Registers   */
        UART    (RW ) : o=004000h l=004000h 	/* UART                     */
        RSV     (R  ) : o=008000h l=004000h 	/* for Duaghtercard         */


}

SECTIONS
{
        .text :  >      DARAM1   PAGE 0
        .word : >       DARAM1   PAGE 0
        .cinit: >       DARAM1   PAGE 0
        .vectors:>       VECS    PAGE 0
        
        .const:  >       DARAM2   PAGE 1
        .bss  :  >       DARAM2   PAGE 1
        
        .stack : >       DARAM2   PAGE 1
        .system: >       DARAM2   PAGE 1
        .data :  >       DARAM2   PAGE 1      
}