uart_rx.v

内含有完整的UART代码

/******************************************************************************
* File:    uart_tb.v
* Version: V0.0
* Author:  minjingguo <[e-mail]>
* Date:    20070814
* Company: SHHIC Co., Ltd.
******************************************************************************
* Description:
* 
*
******************************************************************************
* Version: V0.1
* Modifier: name <email>
* Date:
* Description:
******************************************************************************/
// ************************* 


// *************************    
// MODULE DEFINTION
//**************************

module  uart_rx 
    (
    //INPUTS
    rst     ,
    clk16x  ,
    rd      ,
    rxd     ,
    parity_def,   
    //OUTPUTS
    dout    ,
    dat_rdy ,
    framing_error,
    parity_error
    );
    
// *************************
// INPUTS
// *************************
input           rxd          ;
input           clk16x       ;
input           rst          ;
input           rd           ;
input           parity_def   ;

// *************************
// OUTPUTS 
// *************************
output  [7:0]   dout         ;
output          dat_rdy      ;
output          framing_error;
output          parity_error ;


// *************************
// INTERNAL SIGNALS
// *************************
reg     [7:0]   dout         ;
reg             rxd1         ;
reg             rxd2         ;
reg     [3:0]   cnt_clk      ;
reg     [3:0]   cnt_byte     ;
reg     [7:0]   rsr          ;
reg     [7:0]   rbr          ;
reg             parity       ;
reg             parity_error ;
reg             framing_error;
reg             dat_rdy      ;

// *************************
// CODE
// *************************
always @(posedge clk16x or negedge rst)
begin
    if (rst== 1'h0)
    begin
        dout    <= #1 8'b0 ;
        dat_rdy <= #1 1'b0 ;
    end
    else if (rd)
    begin
        dout    <= #1 dout ;
        dat_rdy  <= #1 1'b0;
    end    
    else if (cnt_byte==4'ha & cnt_clk==4'ha)
    begin
        dout    <= #1 rbr;
        dat_rdy  <= #1 1'b1 ;
    end
end


always @(posedge clk16x or negedge rst)
begin
    if (rst== 1'h0)
    begin
        rxd1    <= #1 1'b1 ;
        rxd2    <= #1 1'b1 ;
    end
    else
    begin
        rxd1    <= #1 rxd  ;
        rxd2    <= #1 rxd1 ;
    end
end

always @(posedge clk16x or negedge rst)
begin
    if (rst== 1'h0)
    begin
        cnt_clk     <= #1 4'hf;
        cnt_byte    <= #1 4'hf;
    end
    else
    begin
        if (cnt_byte==4'hf)
        begin
            if (!rxd1 && rxd2)
            begin
                cnt_clk     <= #1 4'b0;
                cnt_byte    <= #1 4'b0;
            end
        end
        else
        begin
            cnt_clk     <= #1 cnt_clk+1;
            if (cnt_clk==4'hf)
            begin
                if (cnt_byte==4'ha)
                    cnt_byte    <= #1 4'hf;
                else
                    cnt_byte    <= #1 cnt_byte+1;
            end
        end
    end
end

always @(posedge clk16x or negedge rst)
begin
    if (rst== 1'h0)
    begin
        rsr     <= #1 8'b0 ;
        rbr     <= #1 8'b0 ;
        parity  <= #1 1'b1 ;
        framing_error <= #1 1'b0 ;
        parity_error  <= #1 1'b0 ;
    end
    else if (cnt_clk==4'h7)
    begin        
        if (cnt_byte== 4'h0)           
            parity  <= #1 parity_def ;
        else if (cnt_byte >= 4'h1 && cnt_byte <= 4'h8) 
        begin
            rsr[0]  <= #1 rxd2 ;
            rsr[7:1]<= #1 rsr[6:0] ;
            parity  <= #1 parity ^ rxd2 ;
        end
        else if (cnt_byte == 4'h9)
        begin
            rbr     <= #1 rsr ;
            parity_error  <= #1 parity^rxd2;
        end
        else if (cnt_byte == 4'ha)
        begin
            framing_error <= #1 rxd2 ;
        end        
    end
end


endmodule