saa711x_regs.h

来自「trident tm5600的linux驱动」· C头文件 代码 · 共 550 行 · 第 1/2 页

	{ R_1C_ENHAN_COMB_CTRL1, 1,
	 "Enhanced comb ctrl1"},
	{ R_1D_ENHAN_COMB_CTRL2, 1,
	 "Enhanced comb ctrl1"},
	{R_1E_STATUS_BYTE_1_VD_DEC,1,
	 "Status byte 1 video decoder"},
	{R_1F_STATUS_BYTE_2_VD_DEC,1,
	 "Status byte 2 video decoder"},

	/* Component processing and interrupt masking part:  0x20h to R_2F_INTERRUPT_MASK_3 */
	/* 0x20 to 0x22 - Reserved */
	{R_23_INPUT_CNTL_5,1,
	 "Analog input control 5"},
	{R_24_INPUT_CNTL_6,1,
	 "Analog input control 6"},
	{R_25_INPUT_CNTL_7,1,
	 "Analog input control 7"},
	/* 0x26 to 0x28 - Reserved */
	{R_29_COMP_DELAY,1,
	 "Component delay"},
	{R_2A_COMP_BRIGHT_CNTL,1,
	 "Component brightness control"},
	{R_2B_COMP_CONTRAST_CNTL,1,
	 "Component contrast control"},
	{R_2C_COMP_SAT_CNTL,1,
	 "Component saturation control"},
	{R_2D_INTERRUPT_MASK_1,1,
	 "Interrupt mask 1"},
	{R_2E_INTERRUPT_MASK_2,1,
	 "Interrupt mask 2"},
	{R_2F_INTERRUPT_MASK_3,1,
	 "Interrupt mask 3"},

	/* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */
	{R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3,
	 "Audio master clock cycles per field"},
	/* 0x33 - Reserved */
	{R_34_AUD_MAST_CLK_NOMINAL_INC,3,
	 "Audio master clock nominal increment"},
	/* 0x37 - Reserved */
	{R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
	 "Clock ratio AMXCLK to ASCLK"},
	{R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
	 "Clock ratio ASCLK to ALRCLK"},
	{R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
	 "Audio clock generator basic setup"},
	/* 0x3b-0x3f - Reserved */

	/* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */
	{R_40_SLICER_CNTL_1,1,
	 "Slicer control 1"},
	{R_41_LCR,23,
	 "R_41_LCR"},
	{R_58_PROGRAM_FRAMING_CODE,1,
	 "Programmable framing code"},
	{R_59_H_OFF_FOR_SLICER,1,
	 "Horizontal offset for slicer"},
	{R_5A_V_OFF_FOR_SLICER,1,
	 "Vertical offset for slicer"},
	{R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
	 "Field offset and MSBs for horizontal and vertical offset"},
	{R_5D_DID,1,
	 "Header and data identification (R_5D_DID)"},
	{R_5E_SDID,1,
	 "Sliced data identification (R_5E_SDID) code"},
	{R_60_SLICER_STATUS_BYTE_0,1,
	 "Slicer status byte 0"},
	{R_61_SLICER_STATUS_BYTE_1,1,
	 "Slicer status byte 1"},
	{R_62_SLICER_STATUS_BYTE_2,1,
	 "Slicer status byte 2"},
	/* 0x63-0x7f - Reserved */

	/* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
	/* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */
	{R_80_GLOBAL_CNTL_1,1,
	 "Global control 1"},
	{R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
	 "Vertical sync and Field ID source selection, retimed V and F signals"},
	/* 0x82 - Reserved */
	{R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
	 "X port I/O enable and output clock"},
	{R_84_I_PORT_SIGNAL_DEF,1,
	 "I port signal definitions"},
	{R_85_I_PORT_SIGNAL_POLAR,1,
	 "I port signal polarities"},
	{R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
	 "I port FIFO flag control and arbitration"},
	{R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED,  1,
	 "I port I/O enable output clock and gated"},
	{R_88_POWER_SAVE_ADC_PORT_CNTL,1,
	 "Power save/ADC port control"},
	/* 089-0x8e - Reserved */
	{R_8F_STATUS_INFO_SCALER,1,
	 "Status information scaler part"},

	/* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
	/* Task A: Basic settings and acquisition window definition */
	{R_90_A_TASK_HANDLING_CNTL,1,
	 "Task A: Task handling control"},
	{R_91_A_X_PORT_FORMATS_AND_CONF,1,
	 "Task A: X port formats and configuration"},
	{R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
	 "Task A: X port input reference signal definition"},
	{R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
	 "Task A: I port output formats and configuration"},
	{R_94_A_HORIZ_INPUT_WINDOW_START,2,
	 "Task A: Horizontal input window start"},
	{R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2,
	 "Task A: Horizontal input window length"},
	{R_98_A_VERT_INPUT_WINDOW_START,2,
	 "Task A: Vertical input window start"},
	{R_9A_A_VERT_INPUT_WINDOW_LENGTH,2,
	 "Task A: Vertical input window length"},
	{R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
	 "Task A: Horizontal output window length"},
	{R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2,
	 "Task A: Vertical output window length"},

	/* Task A: FIR filtering and prescaling */
	{R_A0_A_HORIZ_PRESCALING,1,
	 "Task A: Horizontal prescaling"},
	{R_A1_A_ACCUMULATION_LENGTH,1,
	 "Task A: Accumulation length"},
	{R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
	 "Task A: Prescaler DC gain and FIR prefilter"},
	/* 0xa3 - Reserved */
	{R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
	 "Task A: Luminance brightness control"},
	{R_A5_A_LUMA_CONTRAST_CNTL,1,
	 "Task A: Luminance contrast control"},
	{R_A6_A_CHROMA_SATURATION_CNTL,1,
	 "Task A: Chrominance saturation control"},
	/* 0xa7 - Reserved */

	/* Task A: Horizontal phase scaling */
	{R_A8_A_HORIZ_LUMA_SCALING_INC,2,
	 "Task A: Horizontal luminance scaling increment"},
	{R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
	 "Task A: Horizontal luminance phase offset"},
	/* 0xab - Reserved */
	{R_AC_A_HORIZ_CHROMA_SCALING_INC,2,
	 "Task A: Horizontal chrominance scaling increment"},
	{R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
	 "Task A: Horizontal chrominance phase offset"},
	/* 0xaf - Reserved */

	/* Task A: Vertical scaling */
	{R_B0_A_VERT_LUMA_SCALING_INC,2,
	 "Task A: Vertical luminance scaling increment"},
	{R_B2_A_VERT_CHROMA_SCALING_INC,2,
	 "Task A: Vertical chrominance scaling increment"},
	{R_B4_A_VERT_SCALING_MODE_CNTL,1,
	 "Task A: Vertical scaling mode control"},
	/* 0xb5-0xb7 - Reserved */
	{R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
	 "Task A: Vertical chrominance phase offset '00'"},
	{R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
	 "Task A: Vertical chrominance phase offset '01'"},
	{R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
	 "Task A: Vertical chrominance phase offset '10'"},
	{R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
	 "Task A: Vertical chrominance phase offset '11'"},
	{R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
	 "Task A: Vertical luminance phase offset '00'"},
	{R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
	 "Task A: Vertical luminance phase offset '01'"},
	{R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
	 "Task A: Vertical luminance phase offset '10'"},
	{R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
	 "Task A: Vertical luminance phase offset '11'"},

	/* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
	/* Task B: Basic settings and acquisition window definition */
	{R_C0_B_TASK_HANDLING_CNTL,1,
	 "Task B: Task handling control"},
	{R_C1_B_X_PORT_FORMATS_AND_CONF,1,
	 "Task B: X port formats and configuration"},
	{R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
	 "Task B: Input reference signal definition"},
	{R_C3_B_I_PORT_FORMATS_AND_CONF,1,
	 "Task B: I port formats and configuration"},
	{R_C4_B_HORIZ_INPUT_WINDOW_START,2,
	 "Task B: Horizontal input window start"},
	{R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2,
	 "Task B: Horizontal input window length"},
	{R_C8_B_VERT_INPUT_WINDOW_START,2,
	 "Task B: Vertical input window start"},
	{R_CA_B_VERT_INPUT_WINDOW_LENGTH,2,
	 "Task B: Vertical input window length"},
	{R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
	 "Task B: Horizontal output window length"},
	{R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2,
	 "Task B: Vertical output window length"},

	/* Task B: FIR filtering and prescaling */
	{R_D0_B_HORIZ_PRESCALING,1,
	 "Task B: Horizontal prescaling"},
	{R_D1_B_ACCUMULATION_LENGTH,1,
	 "Task B: Accumulation length"},
	{R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
	 "Task B: Prescaler DC gain and FIR prefilter"},
	/* 0xd3 - Reserved */
	{R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
	 "Task B: Luminance brightness control"},
	{R_D5_B_LUMA_CONTRAST_CNTL,1,
	 "Task B: Luminance contrast control"},
	{R_D6_B_CHROMA_SATURATION_CNTL,1,
	 "Task B: Chrominance saturation control"},
	/* 0xd7 - Reserved */

	/* Task B: Horizontal phase scaling */
	{R_D8_B_HORIZ_LUMA_SCALING_INC,2,
	 "Task B: Horizontal luminance scaling increment"},
	{R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
	 "Task B: Horizontal luminance phase offset"},
	/* 0xdb - Reserved */
	{R_DC_B_HORIZ_CHROMA_SCALING,2,
	 "Task B: Horizontal chrominance scaling"},
	{R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
	 "Task B: Horizontal Phase Offset Chroma"},
	/* 0xdf - Reserved */

	/* Task B: Vertical scaling */
	{R_E0_B_VERT_LUMA_SCALING_INC,2,
	 "Task B: Vertical luminance scaling increment"},
	{R_E2_B_VERT_CHROMA_SCALING_INC,2,
	 "Task B: Vertical chrominance scaling increment"},
	{R_E4_B_VERT_SCALING_MODE_CNTL,1,
	 "Task B: Vertical scaling mode control"},
	/* 0xe5-0xe7 - Reserved */
	{R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
	 "Task B: Vertical chrominance phase offset '00'"},
	{R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
	 "Task B: Vertical chrominance phase offset '01'"},
	{R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
	 "Task B: Vertical chrominance phase offset '10'"},
	{R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
	 "Task B: Vertical chrominance phase offset '11'"},
	{R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
	 "Task B: Vertical luminance phase offset '00'"},
	{R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
	 "Task B: Vertical luminance phase offset '01'"},
	{R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
	 "Task B: Vertical luminance phase offset '10'"},
	{R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
	 "Task B: Vertical luminance phase offset '11'"},

	/* second PLL (PLL2) and Pulsegenerator Programming */
	{ R_F0_LFCO_PER_LINE, 1,
	  "LFCO's per line"},
	{ R_F1_P_I_PARAM_SELECT,1,
	  "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"},
	{ R_F2_NOMINAL_PLL2_DTO,1,
	 "Nominal PLL2 DTO"},
	{R_F3_PLL_INCREMENT,1,
	 "PLL2 Increment"},
	{R_F4_PLL2_STATUS,1,
	 "PLL2 Status"},
	{R_F5_PULSGEN_LINE_LENGTH,1,
	 "Pulsgen. line length"},
	{R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
	 "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
	{R_F7_PULSE_A_POS_MSB,1,
	 "Pulse A Position"},
	{R_F8_PULSE_B_POS,2,
	 "Pulse B Position"},
	{R_FA_PULSE_C_POS,2,
	 "Pulse C Position"},
	/* 0xfc to 0xfe - Reserved */
	{R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
	 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
};
#endif