drx397xd.c

来自「trident tm5600的linux驱动」· C语言 代码 · 共 1,600 行 · 第 1/3 页

	*lockstat = 0;

	rc = RD16(s, 0x082004b);
	if (rc < 0)
		return rc;

	if (s->config.d60 != 2)
		return 0;

	if ((rc & 7) == 7)
		*lockstat |= 1;
	if ((rc & 3) == 3)
		*lockstat |= 2;
	if (rc & 1)
		*lockstat |= 4;
	return 0;
}

static int CorrectSysClockDeviation(struct drx397xD_state *s)
{
	int rc = -EINVAL;
	int lockstat;
	u32 clk, clk_limit;

	pr_debug("%s\n", __func__);

	if (s->config.d5C == 0) {
		EXIT_RC(WR16(s, 0x08200e8, 0x010));
		EXIT_RC(WR16(s, 0x08200e9, 0x113));
		s->config.d5C = 1;
		return rc;
	}
	if (s->config.d5C != 1)
		goto exit_rc;

	rc = RD16(s, 0x0820048);

	rc = GetLockStatus(s, &lockstat);
	if (rc < 0)
		goto exit_rc;
	if ((lockstat & 1) == 0)
		goto exit_rc;

	EXIT_RC(WR16(s, 0x0420033, 0x200));
	EXIT_RC(WR16(s, 0x0420034, 0xc5));
	EXIT_RC(WR16(s, 0x0420035, 0x10));
	EXIT_RC(WR16(s, 0x0420036, 0x1));
	EXIT_RC(WR16(s, 0x0420037, 0xa));
	EXIT_RC(HI_Command(s, 6));
	EXIT_RC(RD16(s, 0x0420040));
	clk = rc;
	EXIT_RC(RD16(s, 0x0420041));
	clk |= rc << 16;

	if (clk <= 0x26ffff)
		goto exit_rc;
	if (clk > 0x610000)
		goto exit_rc;

	if (!s->bandwidth_parm)
		return -EINVAL;

	/* round & convert to Hz */
	clk = ((u64) (clk + 0x800000) * s->bandwidth_parm + (1 << 20)) >> 21;
	clk_limit = s->config.f_osc * MAX_CLOCK_DRIFT / 1000;

	if (clk - s->config.f_osc * 1000 + clk_limit <= 2 * clk_limit) {
		s->f_osc = clk;
		pr_debug("%s: osc %d %d [Hz]\n", __func__,
			 s->config.f_osc * 1000, clk - s->config.f_osc * 1000);
	}
	rc = WR16(s, 0x08200e8, 0);

exit_rc:
	return rc;
}

static int ConfigureMPEGOutput(struct drx397xD_state *s, int type)
{
	int rc, si, bp;

	pr_debug("%s\n", __func__);

	si = s->config.wA0;
	if (s->config.w98 == 0) {
		si |= 1;
		bp = 0;
	} else {
		si &= ~1;
		bp = 0x200;
	}
	if (s->config.w9A == 0)
		si |= 0x80;
	else
		si &= ~0x80;

	EXIT_RC(WR16(s, 0x2150045, 0));
	EXIT_RC(WR16(s, 0x2150010, si));
	EXIT_RC(WR16(s, 0x2150011, bp));
	rc = WR16(s, 0x2150012, (type == 0 ? 0xfff : 0));

exit_rc:
	return rc;
}

static int drx_tune(struct drx397xD_state *s,
		    struct dvb_frontend_parameters *fep)
{
	u16 v22 = 0;
	u16 v1C = 0;
	u16 v1A = 0;
	u16 v18 = 0;
	u32 edi = 0, ebx = 0, ebp = 0, edx = 0;
	u16 v20 = 0, v1E = 0, v16 = 0, v14 = 0, v12 = 0, v10 = 0, v0E = 0;

	int rc, df_tuner;
	int a, b, c, d;
	pr_debug("%s %d\n", __func__, s->config.d60);

	if (s->config.d60 != 2)
		goto set_tuner;
	rc = CorrectSysClockDeviation(s);
	if (rc < 0)
		goto set_tuner;

	s->config.d60 = 1;
	rc = ConfigureMPEGOutput(s, 0);
	if (rc < 0)
		goto set_tuner;
#if 0

	if (s->chip_rev != DRXD_FW_B1) {
		rc = WR16(s, 0x2150000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x2110000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x0800000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x2800000, 0);
	} else {
		rc = WR16(s, 0x0800000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x2800000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x1000000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x1400000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x1800000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x1c00000, 0);
		if (rc < 0)
			goto loc_800111A;
		rc = WR16(s, 0x2000000, 0);
	}
      loc_800111A:
#endif
set_tuner:

	rc = PLL_Set(s, fep, &df_tuner);
	if (rc < 0) {
		printk(KERN_ERR "Error in pll_set\n");
		goto exit_rc;
	}
	msleep(200);

	a = rc = RD16(s, 0x2150016);
	if (rc < 0)
		goto exit_rc;
	b = rc = RD16(s, 0x2150010);
	if (rc < 0)
		goto exit_rc;
	c = rc = RD16(s, 0x2150034);
	if (rc < 0)
		goto exit_rc;
	d = rc = RD16(s, 0x2150035);
	if (rc < 0)
		goto exit_rc;
	rc = WR16(s, 0x2150014, c);
	rc = WR16(s, 0x2150015, d);
	rc = WR16(s, 0x2150010, 0);
	rc = WR16(s, 0x2150000, 2);
	rc = WR16(s, 0x2150036, 0x0fff);
	rc = WR16(s, 0x2150016, a);

	rc = WR16(s, 0x2150010, 2);
	rc = WR16(s, 0x2150007, 0);
	rc = WR16(s, 0x2150000, 1);
	rc = WR16(s, 0x2110000, 0);
	rc = WR16(s, 0x0800000, 0);
	rc = WR16(s, 0x2800000, 0);
	rc = WR16(s, 0x2110010, 0x664);

	rc = write_fw(s, DRXD_ResetECRAM);
	rc = WR16(s, 0x2110000, 1);

	rc = write_fw(s, DRXD_InitSC);
	if (rc < 0)
		goto exit_rc;

	rc = SetCfgIfAgc(s, &s->config.ifagc);
	if (rc < 0)
		goto exit_rc;

	rc = SetCfgRfAgc(s, &s->config.rfagc);
	if (rc < 0)
		goto exit_rc;

	if (fep->u.ofdm.transmission_mode != TRANSMISSION_MODE_2K)
		v22 = 1;
	switch (fep->u.ofdm.transmission_mode) {
	case TRANSMISSION_MODE_8K:
		edi = 1;
		if (s->chip_rev == DRXD_FW_B1)
			break;

		rc = WR16(s, 0x2010010, 0);
		if (rc < 0)
			break;
		v1C = 0x63;
		v1A = 0x53;
		v18 = 0x43;
		break;
	default:
		edi = 0;
		if (s->chip_rev == DRXD_FW_B1)
			break;

		rc = WR16(s, 0x2010010, 1);
		if (rc < 0)
			break;

		v1C = 0x61;
		v1A = 0x47;
		v18 = 0x41;
	}

	switch (fep->u.ofdm.guard_interval) {
	case GUARD_INTERVAL_1_4:
		edi |= 0x0c;
		break;
	case GUARD_INTERVAL_1_8:
		edi |= 0x08;
		break;
	case GUARD_INTERVAL_1_16:
		edi |= 0x04;
		break;
	case GUARD_INTERVAL_1_32:
		break;
	default:
		v22 |= 2;
	}

	ebx = 0;
	ebp = 0;
	v20 = 0;
	v1E = 0;
	v16 = 0;
	v14 = 0;
	v12 = 0;
	v10 = 0;
	v0E = 0;

	switch (fep->u.ofdm.hierarchy_information) {
	case HIERARCHY_1:
		edi |= 0x40;
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x1c10047, 1);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x2010012, 1);
		if (rc < 0)
			goto exit_rc;
		ebx = 0x19f;
		ebp = 0x1fb;
		v20 = 0x0c0;
		v1E = 0x195;
		v16 = 0x1d6;
		v14 = 0x1ef;
		v12 = 4;
		v10 = 5;
		v0E = 5;
		break;
	case HIERARCHY_2:
		edi |= 0x80;
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x1c10047, 2);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x2010012, 2);
		if (rc < 0)
			goto exit_rc;
		ebx = 0x08f;
		ebp = 0x12f;
		v20 = 0x0c0;
		v1E = 0x11e;
		v16 = 0x1d6;
		v14 = 0x15e;
		v12 = 4;
		v10 = 5;
		v0E = 5;
		break;
	case HIERARCHY_4:
		edi |= 0xc0;
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x1c10047, 3);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x2010012, 3);
		if (rc < 0)
			goto exit_rc;
		ebx = 0x14d;
		ebp = 0x197;
		v20 = 0x0c0;
		v1E = 0x1ce;
		v16 = 0x1d6;
		v14 = 0x11a;
		v12 = 4;
		v10 = 6;
		v0E = 5;
		break;
	default:
		v22 |= 8;
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x1c10047, 0);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x2010012, 0);
		if (rc < 0)
			goto exit_rc;
				/* QPSK    QAM16  QAM64	*/
		ebx = 0x19f;	/*                 62	*/
		ebp = 0x1fb;	/*                 15	*/
		v20 = 0x16a;	/*  62			*/
		v1E = 0x195;	/*         62		*/
		v16 = 0x1bb;	/*  15			*/
		v14 = 0x1ef;	/*         15		*/
		v12 = 5;	/*  16			*/
		v10 = 5;	/*         16		*/
		v0E = 5;	/*                 16	*/
	}

	switch (fep->u.ofdm.constellation) {
	default:
		v22 |= 4;
	case QPSK:
		if (s->chip_rev == DRXD_FW_B1)
			break;

		rc = WR16(s, 0x1c10046, 0);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x2010011, 0);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001a, 0x10);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001b, 0);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001c, 0);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10062, v20);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c1002a, v1C);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10015, v16);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10016, v12);
		if (rc < 0)
			goto exit_rc;
		break;
	case QAM_16:
		edi |= 0x10;
		if (s->chip_rev == DRXD_FW_B1)
			break;

		rc = WR16(s, 0x1c10046, 1);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x2010011, 1);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001a, 0x10);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001b, 4);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001c, 0);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10062, v1E);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c1002a, v1A);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10015, v14);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10016, v10);
		if (rc < 0)
			goto exit_rc;
		break;
	case QAM_64:
		edi |= 0x20;
		rc = WR16(s, 0x1c10046, 2);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x2010011, 2);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001a, 0x20);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001b, 8);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x201001c, 2);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10062, ebx);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c1002a, v18);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10015, ebp);
		if (rc < 0)
			goto exit_rc;
		rc = WR16(s, 0x1c10016, v0E);
		if (rc < 0)
			goto exit_rc;
		break;
	}

	if (s->config.s20d24 == 1) {
		rc = WR16(s, 0x2010013, 0);
	} else {
		rc = WR16(s, 0x2010013, 1);
		edi |= 0x1000;
	}

	switch (fep->u.ofdm.code_rate_HP) {
	default:
		v22 |= 0x10;
	case FEC_1_2:
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x2090011, 0);
		break;
	case FEC_2_3:
		edi |= 0x200;
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x2090011, 1);
		break;
	case FEC_3_4:
		edi |= 0x400;
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x2090011, 2);
		break;
	case FEC_5_6:		/* 5 */
		edi |= 0x600;
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x2090011, 3);
		break;
	case FEC_7_8:		/* 7 */
		edi |= 0x800;
		if (s->chip_rev == DRXD_FW_B1)
			break;
		rc = WR16(s, 0x2090011, 4);
		break;
	};
	if (rc < 0)
		goto exit_rc;

	switch (fep->u.ofdm.bandwidth) {
	default:
		rc = -EINVAL;
		goto exit_rc;
	case BANDWIDTH_8_MHZ:	/* 0 */
	case BANDWIDTH_AUTO:
		rc = WR16(s, 0x0c2003f, 0x32);
		s->bandwidth_parm = ebx = 0x8b8249;
		edx = 0;
		break;
	case BANDWIDTH_7_MHZ:
		rc = WR16(s, 0x0c2003f, 0x3b);
		s->bandwidth_parm = ebx = 0x7a1200;
		edx = 0x4807;
		break;
	case BANDWIDTH_6_MHZ:
		rc = WR16(s, 0x0c2003f, 0x47);
		s->bandwidth_parm = ebx = 0x68a1b6;
		edx = 0x0f07;
		break;
	};

	if (rc < 0)
		goto exit_rc;

	rc = WR16(s, 0x08200ec, edx);
	if (rc < 0)
		goto exit_rc;

	rc = RD16(s, 0x0820050);
	if (rc < 0)
		goto exit_rc;
	rc = WR16(s, 0x0820050, rc);

	{
		/* Configure bandwidth specific factor */
		ebx = div64_u64(((u64) (s->f_osc) << 21) + (ebx >> 1),