s5h1420.c

trident tm5600的linux驱动

	u64 val = 0;
	u8 v;
	int sampling = 2;

	v = s5h1420_readreg(state, QPSK02);
	s5h1420_writereg(state, QPSK02, v | 0x08);
	val  = s5h1420_readreg(state, Tnco01) << 16;
	val |= s5h1420_readreg(state, Tnco02) << 8;
	val |= s5h1420_readreg(state, Tnco03);
	s5h1420_writereg(state, QPSK02, v & 0xf7);

	dprintk("get_symbolrate: raw: %x\n",  val);

	val *= (state->fclk / 1000);
	if (s5h1420_readreg(state, QPSK01) & 0x2)
		do_div(val, 1 << 24);
	else
		do_div(val, 1 << 25);

	dprintk("get_symbolrate: %d\n", (u32) (val * 1000ULL));
	return (u32) (val * 1000ULL);
#endif
	return state->symbol_rate;
}

static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
{
	int val;
	u8 v;

	dprintk("enter %s\n", __func__);

	/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
	 * divide fclk by 1000000 to get the correct value. */
	val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));

	dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);

	v = s5h1420_readreg(state, Loop01);
	s5h1420_writereg(state, Loop01, v & 0xbf);
	s5h1420_writereg(state, Pnco01, val >> 16);
	s5h1420_writereg(state, Pnco02, val >> 8);
	s5h1420_writereg(state, Pnco03, val & 0xff);
	s5h1420_writereg(state, Loop01, v | 0x40);
	dprintk("leave %s\n", __func__);
}

static int s5h1420_getfreqoffset(struct s5h1420_state* state)
{
	int val;

	s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
	val  = s5h1420_readreg(state, 0x0e) << 16;
	val |= s5h1420_readreg(state, 0x0f) << 8;
	val |= s5h1420_readreg(state, 0x10);
	s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);

	if (val & 0x800000)
		val |= 0xff000000;

	/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
	 * divide fclk by 1000000 to get the correct value. */
	val = (((-val) * (state->fclk/1000000)) / (1<<24));

	return val;
}

static void s5h1420_setfec_inversion(struct s5h1420_state* state,
				     struct dvb_frontend_parameters *p)
{
	u8 inversion = 0;
	u8 vit08, vit09;

	dprintk("enter %s\n", __func__);

	if (p->inversion == INVERSION_OFF)
		inversion = state->config->invert ? 0x08 : 0;
	else if (p->inversion == INVERSION_ON)
		inversion = state->config->invert ? 0 : 0x08;

	if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
		vit08 = 0x3f;
		vit09 = 0;
	} else {
		switch(p->u.qpsk.fec_inner) {
		case FEC_1_2:
			vit08 = 0x01; vit09 = 0x10;
			break;

		case FEC_2_3:
			vit08 = 0x02; vit09 = 0x11;
			break;

		case FEC_3_4:
			vit08 = 0x04; vit09 = 0x12;
			break;

		case FEC_5_6:
			vit08 = 0x08; vit09 = 0x13;
			break;

		case FEC_6_7:
			vit08 = 0x10; vit09 = 0x14;
			break;

		case FEC_7_8:
			vit08 = 0x20; vit09 = 0x15;
			break;

		default:
			return;
		}
	}
	vit09 |= inversion;
	dprintk("fec: %02x %02x\n", vit08, vit09);
	s5h1420_writereg(state, Vit08, vit08);
	s5h1420_writereg(state, Vit09, vit09);
	dprintk("leave %s\n", __func__);
}

static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
{
	switch(s5h1420_readreg(state, 0x32) & 0x07) {
	case 0:
		return FEC_1_2;

	case 1:
		return FEC_2_3;

	case 2:
		return FEC_3_4;

	case 3:
		return FEC_5_6;

	case 4:
		return FEC_6_7;

	case 5:
		return FEC_7_8;
	}

	return FEC_NONE;
}

static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
{
	if (s5h1420_readreg(state, 0x32) & 0x08)
		return INVERSION_ON;

	return INVERSION_OFF;
}

static int s5h1420_set_frontend(struct dvb_frontend* fe,
				struct dvb_frontend_parameters *p)
{
	struct s5h1420_state* state = fe->demodulator_priv;
	int frequency_delta;
	struct dvb_frontend_tune_settings fesettings;
	uint8_t clock_settting;

	dprintk("enter %s\n", __func__);

	/* check if we should do a fast-tune */
	memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
	s5h1420_get_tune_settings(fe, &fesettings);
	frequency_delta = p->frequency - state->tunedfreq;
	if ((frequency_delta > -fesettings.max_drift) &&
			(frequency_delta < fesettings.max_drift) &&
			(frequency_delta != 0) &&
			(state->fec_inner == p->u.qpsk.fec_inner) &&
			(state->symbol_rate == p->u.qpsk.symbol_rate)) {

		if (fe->ops.tuner_ops.set_params) {
			fe->ops.tuner_ops.set_params(fe, p);
			if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
		}
		if (fe->ops.tuner_ops.get_frequency) {
			u32 tmp;
			fe->ops.tuner_ops.get_frequency(fe, &tmp);
			if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
			s5h1420_setfreqoffset(state, p->frequency - tmp);
		} else {
			s5h1420_setfreqoffset(state, 0);
		}
		dprintk("simple tune\n");
		return 0;
	}
	dprintk("tuning demod\n");

	/* first of all, software reset */
	s5h1420_reset(state);

	/* set s5h1420 fclk PLL according to desired symbol rate */
	if (p->u.qpsk.symbol_rate > 33000000)
		state->fclk = 80000000;
	else if (p->u.qpsk.symbol_rate > 28500000)
		state->fclk = 59000000;
	else if (p->u.qpsk.symbol_rate > 25000000)
		state->fclk = 86000000;
	else if (p->u.qpsk.symbol_rate > 1900000)
		state->fclk = 88000000;
	else
		state->fclk = 44000000;

	/* Clock */
	switch (state->fclk) {
	default:
	case 88000000:
		clock_settting = 80;
		break;
	case 86000000:
		clock_settting = 78;
		break;
	case 80000000:
		clock_settting = 72;
		break;
	case 59000000:
		clock_settting = 51;
		break;
	case 44000000:
		clock_settting = 36;
		break;
	}
	dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
	s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
	s5h1420_writereg(state, PLL02, 0x40);
	s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));

	/* TODO DC offset removal, config parameter ? */
	if (p->u.qpsk.symbol_rate > 29000000)
		s5h1420_writereg(state, QPSK01, 0xae | 0x10);
	else
		s5h1420_writereg(state, QPSK01, 0xac | 0x10);

	/* set misc registers */
	s5h1420_writereg(state, CON_1, 0x00);
	s5h1420_writereg(state, QPSK02, 0x00);
	s5h1420_writereg(state, Pre01, 0xb0);

	s5h1420_writereg(state, Loop01, 0xF0);
	s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
	s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
	if (p->u.qpsk.symbol_rate > 20000000)
		s5h1420_writereg(state, Loop04, 0x79);
	else
		s5h1420_writereg(state, Loop04, 0x58);
	s5h1420_writereg(state, Loop05, 0x6b);

	if (p->u.qpsk.symbol_rate >= 8000000)
		s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
	else if (p->u.qpsk.symbol_rate >= 4000000)
		s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
	else
		s5h1420_writereg(state, Post01, (3 << 6) | 0x10);

	s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */

	s5h1420_writereg(state, Sync01, 0x33);
	s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
	s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
	s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */

	s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
	s5h1420_writereg(state, DiS03, 0x00);
	s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */

	/* set tuner PLL */
	if (fe->ops.tuner_ops.set_params) {
		fe->ops.tuner_ops.set_params(fe, p);
		if (fe->ops.i2c_gate_ctrl)
			fe->ops.i2c_gate_ctrl(fe, 0);
		s5h1420_setfreqoffset(state, 0);
	}

	/* set the reset of the parameters */
	s5h1420_setsymbolrate(state, p);
	s5h1420_setfec_inversion(state, p);

	/* start QPSK */
	s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);

	state->fec_inner = p->u.qpsk.fec_inner;
	state->symbol_rate = p->u.qpsk.symbol_rate;
	state->postlocked = 0;
	state->tunedfreq = p->frequency;

	dprintk("leave %s\n", __func__);
	return 0;
}

static int s5h1420_get_frontend(struct dvb_frontend* fe,
				struct dvb_frontend_parameters *p)
{
	struct s5h1420_state* state = fe->demodulator_priv;

	p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
	p->inversion = s5h1420_getinversion(state);
	p->u.qpsk.symbol_rate = s5h1420_getsymbolrate(state);
	p->u.qpsk.fec_inner = s5h1420_getfec(state);

	return 0;
}

static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
				     struct dvb_frontend_tune_settings* fesettings)
{
	if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) {
		fesettings->min_delay_ms = 50;
		fesettings->step_size = 2000;
		fesettings->max_drift = 8000;
	} else if (fesettings->parameters.u.qpsk.symbol_rate > 12000000) {
		fesettings->min_delay_ms = 100;
		fesettings->step_size = 1500;
		fesettings->max_drift = 9000;
	} else if (fesettings->parameters.u.qpsk.symbol_rate > 8000000) {
		fesettings->min_delay_ms = 100;
		fesettings->step_size = 1000;
		fesettings->max_drift = 8000;
	} else if (fesettings->parameters.u.qpsk.symbol_rate > 4000000) {
		fesettings->min_delay_ms = 100;
		fesettings->step_size = 500;
		fesettings->max_drift = 7000;
	} else if (fesettings->parameters.u.qpsk.symbol_rate > 2000000) {
		fesettings->min_delay_ms = 200;
		fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000);
		fesettings->max_drift = 14 * fesettings->step_size;
	} else {
		fesettings->min_delay_ms = 200;
		fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000);
		fesettings->max_drift = 18 * fesettings->step_size;
	}

	return 0;
}

static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
	struct s5h1420_state* state = fe->demodulator_priv;

	if (enable)
		return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
	else
		return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
}

static int s5h1420_init (struct dvb_frontend* fe)
{
	struct s5h1420_state* state = fe->demodulator_priv;

	/* disable power down and do reset */
	state->CON_1_val = state->config->serial_mpeg << 4;
	s5h1420_writereg(state, 0x02, state->CON_1_val);
	msleep(10);
	s5h1420_reset(state);

	return 0;
}

static int s5h1420_sleep(struct dvb_frontend* fe)
{
	struct s5h1420_state* state = fe->demodulator_priv;
	state->CON_1_val = 0x12;
	return s5h1420_writereg(state, 0x02, state->CON_1_val);
}

static void s5h1420_release(struct dvb_frontend* fe)
{
	struct s5h1420_state* state = fe->demodulator_priv;
	i2c_del_adapter(&state->tuner_i2c_adapter);
	kfree(state);
}

static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_I2C;
}

static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
{
	struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
	struct i2c_msg m[1 + num];
	u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */

	memset(m, 0, sizeof(struct i2c_msg) * (1 + num));

	m[0].addr = state->config->demod_address;
	m[0].buf  = tx_open;
	m[0].len  = 2;

	memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);

	return i2c_transfer(state->i2c, m, 1+num) == 1 + num ? num : -EIO;
}

static struct i2c_algorithm s5h1420_tuner_i2c_algo = {
	.master_xfer   = s5h1420_tuner_i2c_tuner_xfer,
	.functionality = s5h1420_tuner_i2c_func,
};

struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
{
	struct s5h1420_state *state = fe->demodulator_priv;
	return &state->tuner_i2c_adapter;
}
EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);

static struct dvb_frontend_ops s5h1420_ops;

struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
				    struct i2c_adapter *i2c)
{
	/* allocate memory for the internal state */
	struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
	u8 i;

	if (state == NULL)
		goto error;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	state->postlocked = 0;
	state->fclk = 88000000;
	state->tunedfreq = 0;
	state->fec_inner = FEC_NONE;
	state->symbol_rate = 0;

	/* check if the demod is there + identify it */
	i = s5h1420_readreg(state, ID01);
	if (i != 0x03)
		goto error;

	memset(state->shadow, 0xff, sizeof(state->shadow));

	for (i = 0; i < 0x50; i++)
		state->shadow[i] = s5h1420_readreg(state, i);

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
	state->frontend.demodulator_priv = state;

	/* create tuner i2c adapter */
	strlcpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
		sizeof(state->tuner_i2c_adapter.name));
	state->tuner_i2c_adapter.class     = I2C_CLASS_TV_DIGITAL,
	state->tuner_i2c_adapter.algo      = &s5h1420_tuner_i2c_algo;
	state->tuner_i2c_adapter.algo_data = NULL;
	i2c_set_adapdata(&state->tuner_i2c_adapter, state);
	if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
		printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
		goto error;
	}

	return &state->frontend;

error:
	kfree(state);
	return NULL;
}
EXPORT_SYMBOL(s5h1420_attach);

static struct dvb_frontend_ops s5h1420_ops = {

	.info = {
		.name     = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
		.type     = FE_QPSK,
		.frequency_min    = 950000,
		.frequency_max    = 2150000,
		.frequency_stepsize = 125,     /* kHz for QPSK frontends */
		.frequency_tolerance  = 29500,
		.symbol_rate_min  = 1000000,
		.symbol_rate_max  = 45000000,
		/*  .symbol_rate_tolerance  = ???,*/
		.caps = FE_CAN_INVERSION_AUTO |
		FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
		FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
		FE_CAN_QPSK
	},

	.release = s5h1420_release,

	.init = s5h1420_init,
	.sleep = s5h1420_sleep,
	.i2c_gate_ctrl = s5h1420_i2c_gate_ctrl,

	.set_frontend = s5h1420_set_frontend,
	.get_frontend = s5h1420_get_frontend,
	.get_tune_settings = s5h1420_get_tune_settings,

	.read_status = s5h1420_read_status,
	.read_ber = s5h1420_read_ber,
	.read_signal_strength = s5h1420_read_signal_strength,
	.read_ucblocks = s5h1420_read_ucblocks,

	.diseqc_send_master_cmd = s5h1420_send_master_cmd,
	.diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
	.diseqc_send_burst = s5h1420_send_burst,
	.set_tone = s5h1420_set_tone,
	.set_voltage = s5h1420_set_voltage,
};

MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
MODULE_LICENSE("GPL");