af9005-fe.c

trident tm5600的linux驱动

	    af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
				      &if_gain);
	if (ret)
		return ret;
	/* this value has no real meaning, but i don't have the tables that relate
	   the rf and if gain with the dbm, so I just scale the value */
	*strength = (512 - rf_gain - if_gain) << 7;
	return 0;
}

static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
{
	/* the snr can be derived from the ber and the constellation
	   but I don't think this kind of complex calculations belong
	   in the driver. I may be wrong.... */
	return -ENOSYS;
}

static int af9005_fe_program_cfoe(struct dvb_usb_device *d, fe_bandwidth_t bw)
{
	u8 temp0, temp1, temp2, temp3, buf[4];
	int ret;
	u32 NS_coeff1_2048Nu;
	u32 NS_coeff1_8191Nu;
	u32 NS_coeff1_8192Nu;
	u32 NS_coeff1_8193Nu;
	u32 NS_coeff2_2k;
	u32 NS_coeff2_8k;

	switch (bw) {
	case BANDWIDTH_6_MHZ:
		NS_coeff1_2048Nu = 0x2ADB6DC;
		NS_coeff1_8191Nu = 0xAB7313;
		NS_coeff1_8192Nu = 0xAB6DB7;
		NS_coeff1_8193Nu = 0xAB685C;
		NS_coeff2_2k = 0x156DB6E;
		NS_coeff2_8k = 0x55B6DC;
		break;

	case BANDWIDTH_7_MHZ:
		NS_coeff1_2048Nu = 0x3200001;
		NS_coeff1_8191Nu = 0xC80640;
		NS_coeff1_8192Nu = 0xC80000;
		NS_coeff1_8193Nu = 0xC7F9C0;
		NS_coeff2_2k = 0x1900000;
		NS_coeff2_8k = 0x640000;
		break;

	case BANDWIDTH_8_MHZ:
		NS_coeff1_2048Nu = 0x3924926;
		NS_coeff1_8191Nu = 0xE4996E;
		NS_coeff1_8192Nu = 0xE49249;
		NS_coeff1_8193Nu = 0xE48B25;
		NS_coeff2_2k = 0x1C92493;
		NS_coeff2_8k = 0x724925;
		break;
	default:
		err("Invalid bandwith %d.", bw);
		return -EINVAL;
	}

	/*
	 *  write NS_coeff1_2048Nu
	 */

	temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
	temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
	temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
	temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);

	/*  big endian to make 8051 happy */
	buf[0] = temp3;
	buf[1] = temp2;
	buf[2] = temp1;
	buf[3] = temp0;

	/*  cfoe_NS_2k_coeff1_25_24 */
	ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
	if (ret)
		return ret;

	/*  cfoe_NS_2k_coeff1_23_16 */
	ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
	if (ret)
		return ret;

	/*  cfoe_NS_2k_coeff1_15_8 */
	ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
	if (ret)
		return ret;

	/*  cfoe_NS_2k_coeff1_7_0 */
	ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
	if (ret)
		return ret;

	/*
	 *  write NS_coeff2_2k
	 */

	temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
	temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
	temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
	temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);

	/*  big endian to make 8051 happy */
	buf[0] = temp3;
	buf[1] = temp2;
	buf[2] = temp1;
	buf[3] = temp0;

	ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
	if (ret)
		return ret;

	/*
	 *  write NS_coeff1_8191Nu
	 */

	temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
	temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
	temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
	temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);

	/*  big endian to make 8051 happy */
	buf[0] = temp3;
	buf[1] = temp2;
	buf[2] = temp1;
	buf[3] = temp0;

	ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
	if (ret)
		return ret;

	/*
	 *  write NS_coeff1_8192Nu
	 */

	temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
	temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
	temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
	temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);

	/*  big endian to make 8051 happy */
	buf[0] = temp3;
	buf[1] = temp2;
	buf[2] = temp1;
	buf[3] = temp0;

	ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
	if (ret)
		return ret;

	/*
	 *  write NS_coeff1_8193Nu
	 */

	temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
	temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
	temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
	temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);

	/*  big endian to make 8051 happy */
	buf[0] = temp3;
	buf[1] = temp2;
	buf[2] = temp1;
	buf[3] = temp0;

	ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
	if (ret)
		return ret;

	/*
	 *  write NS_coeff2_8k
	 */

	temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
	temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
	temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
	temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);

	/*  big endian to make 8051 happy */
	buf[0] = temp3;
	buf[1] = temp2;
	buf[2] = temp1;
	buf[3] = temp0;

	ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
	if (ret)
		return ret;

	ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
	return ret;

}

static int af9005_fe_select_bw(struct dvb_usb_device *d, fe_bandwidth_t bw)
{
	u8 temp;
	switch (bw) {
	case BANDWIDTH_6_MHZ:
		temp = 0;
		break;
	case BANDWIDTH_7_MHZ:
		temp = 1;
		break;
	case BANDWIDTH_8_MHZ:
		temp = 2;
		break;
	default:
		err("Invalid bandwith %d.", bw);
		return -EINVAL;
	}
	return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
					  reg_bw_len, temp);
}

static int af9005_fe_power(struct dvb_frontend *fe, int on)
{
	struct af9005_fe_state *state = fe->demodulator_priv;
	u8 temp = on;
	int ret;
	deb_info("power %s tuner\n", on ? "on" : "off");
	ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
#if 0
	if (ret)
		return ret;
	if (fe->ops.tuner_ops.init != NULL) {
		if (on)
			ret = fe->ops.tuner_ops.init(fe);
		else
			ret = fe->ops.tuner_ops.sleep(fe);
	}
#endif
	return ret;
}

static struct mt2060_config af9005_mt2060_config = {
	0xC0
};

static struct qt1010_config af9005_qt1010_config = {
	0xC4
};

static int af9005_fe_init(struct dvb_frontend *fe)
{
	struct af9005_fe_state *state = fe->demodulator_priv;
	struct dvb_usb_adapter *adap = fe->dvb->priv;
	int ret, i, scriptlen;
	u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
	u8 buf[2];
	u16 if1;

	deb_info("in af9005_fe_init\n");

	/* reset */
	deb_info("reset\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
					4, 1, 0x01)))
		return ret;
	if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
		return ret;
	/* clear ofdm reset */
	deb_info("clear ofdm reset\n");
	for (i = 0; i < 150; i++) {
		if ((ret =
		     af9005_read_ofdm_register(state->d,
					       xd_I2C_reg_ofdm_rst, &temp)))
			return ret;
		if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
			break;
		msleep(10);
	}
	if (i == 150)
		return -ETIMEDOUT;

	/*FIXME in the dump
	   write B200 A9
	   write xd_g_reg_ofsm_clk 7
	   read eepr c6 (2)
	   read eepr c7 (2)
	   misc ctrl 3 -> 1
	   read eepr ca (6)
	   write xd_g_reg_ofsm_clk 0
	   write B200 a1
	 */
	ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
	if (ret)
		return ret;
	ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
	if (ret)
		return ret;
	temp = 0x01;
	ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
	if (ret)
		return ret;
	ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
	if (ret)
		return ret;
	ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
	if (ret)
		return ret;

	temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
	if ((ret =
	     af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
					reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
		return ret;
	ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
					 reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);

	if (ret)
		return ret;
	/* don't know what register aefc is, but this is what the windows driver does */
	ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
	if (ret)
		return ret;

	/* set stand alone chip */
	deb_info("set stand alone chip\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
					reg_dca_stand_alone_pos,
					reg_dca_stand_alone_len, 1)))
		return ret;

	/* set dca upper & lower chip */
	deb_info("set dca upper & lower chip\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
					reg_dca_upper_chip_pos,
					reg_dca_upper_chip_len, 0)))
		return ret;
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
					reg_dca_lower_chip_pos,
					reg_dca_lower_chip_len, 0)))
		return ret;

	/* set 2wire master clock to 0x14 (for 60KHz) */
	deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
	if ((ret =
	     af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
		return ret;

	/* clear dca enable chip */
	deb_info("clear dca enable chip\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_dca_en,
					reg_dca_en_pos, reg_dca_en_len, 0)))
		return ret;
#if 0
	/*FIXME in the sample code but not in the captured data */
	/* set B202[7] (1 for DCA, 0 for stand-alone) */
	deb_info("set b202[7]\n");
	if ((ret = af9005_write_register_bits(state->d, 0xb202, 7, 1, 0)))
		return ret;

	/* set A160[4] (1 for DCA & upper, 0 otherwise) */
	deb_info("set a160[4]\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_dca_platch,
					reg_dca_platch_pos,
					reg_dca_platch_len, 0)))
		return ret;

	/* reset tpsrdy bit */
	deb_info("reset tpsrdy bit\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_dca_api_tpsrdy,
					reg_dca_api_tpsrdy_pos,
					reg_dca_api_tpsrdy_len, 0)))
		return ret;
#endif
	/* FIXME these are register bits, but I don't know which ones */
	ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
	if (ret)
		return ret;
	ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
	if (ret)
		return ret;

	/* init other parameters: program cfoe and select bandwith */
	deb_info("program cfoe\n");
	if ((ret = af9005_fe_program_cfoe(state->d, BANDWIDTH_6_MHZ)))
		return ret;
#if 0
	/*FIXME not found in the captured data */
	deb_info("select bandwith\n");
	if ((ret = af9005_fe_select_bw(state->d, BANDWITH_6_MHZ)))	/* FIXME */
		return ret;
#endif
	/* set read-update bit for constellation */
	deb_info("set read-update bit for constellation\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
					reg_feq_read_update_pos,
					reg_feq_read_update_len, 1)))
		return ret;

	/* sample code has a set MPEG TS code here
	   but sniffing reveals that it doesn't do it */

	/* set read-update bit to 1 for DCA constellation */
	deb_info("set read-update bit 1 for DCA constellation\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
					reg_dca_read_update_pos,
					reg_dca_read_update_len, 1)))
		return ret;

	/* enable fec monitor */
	deb_info("enable fec monitor\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
					fec_vtb_rsd_mon_en_pos,
					fec_vtb_rsd_mon_en_len, 1)))
		return ret;

	/* FIXME should be register bits, I don't know which ones */
	ret = af9005_write_ofdm_register(state->d, 0xa601, 0);

#if 0
	/* set register-out bit to 1 for i2c master */
	/* FIXME not in the captured data */
	deb_info("set register-out bit to 1 for i2c master\n");
	if ((ret =
	     af9005_write_register_bits(state->d, xd_p_reg_top_gpioon0,
					reg_top_gpioon0_pos,
					reg_top_gpioon0_len, 1)))
		return ret;
#endif
	/* set api_retrain_never_freeze */
	deb_info("set api_retrain_never_freeze\n");
	if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
		return ret;

	/* load init script */
	deb_info("load init script\n");
	scriptlen = sizeof(script) / sizeof(RegDesc);
	for (i = 0; i < scriptlen; i++) {
		if ((ret =
		     af9005_write_register_bits(state->d, script[i].reg,
						script[i].pos,
						script[i].len, script[i].val)))
			return ret;
		/* save 3 bytes of original fcw */
		if (script[i].reg == 0xae18)
			temp2 = script[i].val;
		if (script[i].reg == 0xae19)
			temp1 = script[i].val;
		if (script[i].reg == 0xae1a)
			temp0 = script[i].val;

		/* save original unplug threshold */
		if (script[i].reg == xd_p_reg_unplug_th)
			state->original_if_unplug_th = script[i].val;
		if (script[i].reg == xd_p_reg_unplug_rf_gain_th)
			state->original_rf_unplug_th = script[i].val;
		if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th)
			state->original_dtop_if_unplug_th = script[i].val;
		if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th)
			state->original_dtop_rf_unplug_th = script[i].val;

	}
	state->original_fcw =
	    ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;

#if 0
	/* power on tuner */
	/*FIXME not in the captured data */
	ret = af9005_fe_power(fe, 1);
	if (ret)
		return ret;
	msleep(100);
#endif

	/* save original TOPs */
	deb_info("save original TOPs\n");

	/*  RF TOP */
	ret =
	    af9005_read_word_agc(state->d,
				 xd_p_reg_aagc_rf_top_numerator_9_8,
				 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
				 &state->original_rf_top);