af9005.h

trident tm5600的linux驱动

#define xd_r_ste_H3	0xA22E
#define	ste_H3_pos 0
#define	ste_H3_len 7
#define	ste_H3_lsb 0
#define xd_r_ste_H4	0xA22F
#define	ste_H4_pos 0
#define	ste_H4_len 7
#define	ste_H4_lsb 0
#define xd_r_ste_Corr_value_I_7_0	0xA230
#define	ste_Corr_value_I_7_0_pos 0
#define	ste_Corr_value_I_7_0_len 8
#define	ste_Corr_value_I_7_0_lsb 0
#define xd_r_ste_Corr_value_I_15_8	0xA231
#define	ste_Corr_value_I_15_8_pos 0
#define	ste_Corr_value_I_15_8_len 8
#define	ste_Corr_value_I_15_8_lsb 8
#define xd_r_ste_Corr_value_I_23_16	0xA232
#define	ste_Corr_value_I_23_16_pos 0
#define	ste_Corr_value_I_23_16_len 8
#define	ste_Corr_value_I_23_16_lsb 16
#define xd_r_ste_Corr_value_I_27_24	0xA233
#define	ste_Corr_value_I_27_24_pos 0
#define	ste_Corr_value_I_27_24_len 4
#define	ste_Corr_value_I_27_24_lsb 24
#define xd_r_ste_Corr_value_Q_7_0	0xA234
#define	ste_Corr_value_Q_7_0_pos 0
#define	ste_Corr_value_Q_7_0_len 8
#define	ste_Corr_value_Q_7_0_lsb 0
#define xd_r_ste_Corr_value_Q_15_8	0xA235
#define	ste_Corr_value_Q_15_8_pos 0
#define	ste_Corr_value_Q_15_8_len 8
#define	ste_Corr_value_Q_15_8_lsb 8
#define xd_r_ste_Corr_value_Q_23_16	0xA236
#define	ste_Corr_value_Q_23_16_pos 0
#define	ste_Corr_value_Q_23_16_len 8
#define	ste_Corr_value_Q_23_16_lsb 16
#define xd_r_ste_Corr_value_Q_27_24	0xA237
#define	ste_Corr_value_Q_27_24_pos 0
#define	ste_Corr_value_Q_27_24_len 4
#define	ste_Corr_value_Q_27_24_lsb 24
#define xd_r_ste_J_num_7_0	0xA238
#define	ste_J_num_7_0_pos 0
#define	ste_J_num_7_0_len 8
#define	ste_J_num_7_0_lsb 0
#define xd_r_ste_J_num_15_8	0xA239
#define	ste_J_num_15_8_pos 0
#define	ste_J_num_15_8_len 8
#define	ste_J_num_15_8_lsb 8
#define xd_r_ste_J_num_23_16	0xA23A
#define	ste_J_num_23_16_pos 0
#define	ste_J_num_23_16_len 8
#define	ste_J_num_23_16_lsb 16
#define xd_r_ste_J_num_31_24	0xA23B
#define	ste_J_num_31_24_pos 0
#define	ste_J_num_31_24_len 8
#define	ste_J_num_31_24_lsb 24
#define xd_r_ste_J_den_7_0	0xA23C
#define	ste_J_den_7_0_pos 0
#define	ste_J_den_7_0_len 8
#define	ste_J_den_7_0_lsb 0
#define xd_r_ste_J_den_15_8	0xA23D
#define	ste_J_den_15_8_pos 0
#define	ste_J_den_15_8_len 8
#define	ste_J_den_15_8_lsb 8
#define xd_r_ste_J_den_18_16	0xA23E
#define	ste_J_den_18_16_pos 0
#define	ste_J_den_18_16_len 3
#define	ste_J_den_18_16_lsb 16
#define xd_r_ste_Beacon_Indicator	0xA23E
#define	ste_Beacon_Indicator_pos 4
#define	ste_Beacon_Indicator_len 1
#define	ste_Beacon_Indicator_lsb 0
#define xd_r_tpsd_Frame_Num	0xA250
#define	tpsd_Frame_Num_pos 0
#define	tpsd_Frame_Num_len 2
#define	tpsd_Frame_Num_lsb 0
#define xd_r_tpsd_Constel	0xA250
#define	tpsd_Constel_pos 2
#define	tpsd_Constel_len 2
#define	tpsd_Constel_lsb 0
#define xd_r_tpsd_GI	0xA250
#define	tpsd_GI_pos 4
#define	tpsd_GI_len 2
#define	tpsd_GI_lsb 0
#define xd_r_tpsd_Mode	0xA250
#define	tpsd_Mode_pos 6
#define	tpsd_Mode_len 2
#define	tpsd_Mode_lsb 0
#define xd_r_tpsd_CR_HP	0xA251
#define	tpsd_CR_HP_pos 0
#define	tpsd_CR_HP_len 3
#define	tpsd_CR_HP_lsb 0
#define xd_r_tpsd_CR_LP	0xA251
#define	tpsd_CR_LP_pos 3
#define	tpsd_CR_LP_len 3
#define	tpsd_CR_LP_lsb 0
#define xd_r_tpsd_Hie	0xA252
#define	tpsd_Hie_pos 0
#define	tpsd_Hie_len 3
#define	tpsd_Hie_lsb 0
#define xd_r_tpsd_Res_Bits	0xA252
#define	tpsd_Res_Bits_pos 3
#define	tpsd_Res_Bits_len 5
#define	tpsd_Res_Bits_lsb 0
#define xd_r_tpsd_Res_Bits_0	0xA253
#define	tpsd_Res_Bits_0_pos 0
#define	tpsd_Res_Bits_0_len 1
#define	tpsd_Res_Bits_0_lsb 0
#define xd_r_tpsd_LengthInd	0xA253
#define	tpsd_LengthInd_pos 1
#define	tpsd_LengthInd_len 6
#define	tpsd_LengthInd_lsb 0
#define xd_r_tpsd_Cell_Id_7_0	0xA254
#define	tpsd_Cell_Id_7_0_pos 0
#define	tpsd_Cell_Id_7_0_len 8
#define	tpsd_Cell_Id_7_0_lsb 0
#define xd_r_tpsd_Cell_Id_15_8	0xA255
#define	tpsd_Cell_Id_15_8_pos 0
#define	tpsd_Cell_Id_15_8_len 8
#define	tpsd_Cell_Id_15_8_lsb 0
#define xd_p_reg_fft_mask_tone0_7_0	0xA260
#define	reg_fft_mask_tone0_7_0_pos 0
#define	reg_fft_mask_tone0_7_0_len 8
#define	reg_fft_mask_tone0_7_0_lsb 0
#define xd_p_reg_fft_mask_tone0_12_8	0xA261
#define	reg_fft_mask_tone0_12_8_pos 0
#define	reg_fft_mask_tone0_12_8_len 5
#define	reg_fft_mask_tone0_12_8_lsb 8
#define xd_p_reg_fft_mask_tone1_7_0	0xA262
#define	reg_fft_mask_tone1_7_0_pos 0
#define	reg_fft_mask_tone1_7_0_len 8
#define	reg_fft_mask_tone1_7_0_lsb 0
#define xd_p_reg_fft_mask_tone1_12_8	0xA263
#define	reg_fft_mask_tone1_12_8_pos 0
#define	reg_fft_mask_tone1_12_8_len 5
#define	reg_fft_mask_tone1_12_8_lsb 8
#define xd_p_reg_fft_mask_tone2_7_0	0xA264
#define	reg_fft_mask_tone2_7_0_pos 0
#define	reg_fft_mask_tone2_7_0_len 8
#define	reg_fft_mask_tone2_7_0_lsb 0
#define xd_p_reg_fft_mask_tone2_12_8	0xA265
#define	reg_fft_mask_tone2_12_8_pos 0
#define	reg_fft_mask_tone2_12_8_len 5
#define	reg_fft_mask_tone2_12_8_lsb 8
#define xd_p_reg_fft_mask_tone3_7_0	0xA266
#define	reg_fft_mask_tone3_7_0_pos 0
#define	reg_fft_mask_tone3_7_0_len 8
#define	reg_fft_mask_tone3_7_0_lsb 0
#define xd_p_reg_fft_mask_tone3_12_8	0xA267
#define	reg_fft_mask_tone3_12_8_pos 0
#define	reg_fft_mask_tone3_12_8_len 5
#define	reg_fft_mask_tone3_12_8_lsb 8
#define xd_p_reg_fft_mask_from0_7_0	0xA268
#define	reg_fft_mask_from0_7_0_pos 0
#define	reg_fft_mask_from0_7_0_len 8
#define	reg_fft_mask_from0_7_0_lsb 0
#define xd_p_reg_fft_mask_from0_12_8	0xA269
#define	reg_fft_mask_from0_12_8_pos 0
#define	reg_fft_mask_from0_12_8_len 5
#define	reg_fft_mask_from0_12_8_lsb 8
#define xd_p_reg_fft_mask_to0_7_0	0xA26A
#define	reg_fft_mask_to0_7_0_pos 0
#define	reg_fft_mask_to0_7_0_len 8
#define	reg_fft_mask_to0_7_0_lsb 0
#define xd_p_reg_fft_mask_to0_12_8	0xA26B
#define	reg_fft_mask_to0_12_8_pos 0
#define	reg_fft_mask_to0_12_8_len 5
#define	reg_fft_mask_to0_12_8_lsb 8
#define xd_p_reg_fft_mask_from1_7_0	0xA26C
#define	reg_fft_mask_from1_7_0_pos 0
#define	reg_fft_mask_from1_7_0_len 8
#define	reg_fft_mask_from1_7_0_lsb 0
#define xd_p_reg_fft_mask_from1_12_8	0xA26D
#define	reg_fft_mask_from1_12_8_pos 0
#define	reg_fft_mask_from1_12_8_len 5
#define	reg_fft_mask_from1_12_8_lsb 8
#define xd_p_reg_fft_mask_to1_7_0	0xA26E
#define	reg_fft_mask_to1_7_0_pos 0
#define	reg_fft_mask_to1_7_0_len 8
#define	reg_fft_mask_to1_7_0_lsb 0
#define xd_p_reg_fft_mask_to1_12_8	0xA26F
#define	reg_fft_mask_to1_12_8_pos 0
#define	reg_fft_mask_to1_12_8_len 5
#define	reg_fft_mask_to1_12_8_lsb 8
#define xd_p_reg_cge_idx0_7_0	0xA280
#define	reg_cge_idx0_7_0_pos 0
#define	reg_cge_idx0_7_0_len 8
#define	reg_cge_idx0_7_0_lsb 0
#define xd_p_reg_cge_idx0_12_8	0xA281
#define	reg_cge_idx0_12_8_pos 0
#define	reg_cge_idx0_12_8_len 5
#define	reg_cge_idx0_12_8_lsb 8
#define xd_p_reg_cge_idx1_7_0	0xA282
#define	reg_cge_idx1_7_0_pos 0
#define	reg_cge_idx1_7_0_len 8
#define	reg_cge_idx1_7_0_lsb 0
#define xd_p_reg_cge_idx1_12_8	0xA283
#define	reg_cge_idx1_12_8_pos 0
#define	reg_cge_idx1_12_8_len 5
#define	reg_cge_idx1_12_8_lsb 8
#define xd_p_reg_cge_idx2_7_0	0xA284
#define	reg_cge_idx2_7_0_pos 0
#define	reg_cge_idx2_7_0_len 8
#define	reg_cge_idx2_7_0_lsb 0
#define xd_p_reg_cge_idx2_12_8	0xA285
#define	reg_cge_idx2_12_8_pos 0
#define	reg_cge_idx2_12_8_len 5
#define	reg_cge_idx2_12_8_lsb 8
#define xd_p_reg_cge_idx3_7_0	0xA286
#define	reg_cge_idx3_7_0_pos 0
#define	reg_cge_idx3_7_0_len 8
#define	reg_cge_idx3_7_0_lsb 0
#define xd_p_reg_cge_idx3_12_8	0xA287
#define	reg_cge_idx3_12_8_pos 0
#define	reg_cge_idx3_12_8_len 5
#define	reg_cge_idx3_12_8_lsb 8
#define xd_p_reg_cge_idx4_7_0	0xA288
#define	reg_cge_idx4_7_0_pos 0
#define	reg_cge_idx4_7_0_len 8
#define	reg_cge_idx4_7_0_lsb 0
#define xd_p_reg_cge_idx4_12_8	0xA289
#define	reg_cge_idx4_12_8_pos 0
#define	reg_cge_idx4_12_8_len 5
#define	reg_cge_idx4_12_8_lsb 8
#define xd_p_reg_cge_idx5_7_0	0xA28A
#define	reg_cge_idx5_7_0_pos 0
#define	reg_cge_idx5_7_0_len 8
#define	reg_cge_idx5_7_0_lsb 0
#define xd_p_reg_cge_idx5_12_8	0xA28B
#define	reg_cge_idx5_12_8_pos 0
#define	reg_cge_idx5_12_8_len 5
#define	reg_cge_idx5_12_8_lsb 8
#define xd_p_reg_cge_idx6_7_0	0xA28C
#define	reg_cge_idx6_7_0_pos 0
#define	reg_cge_idx6_7_0_len 8
#define	reg_cge_idx6_7_0_lsb 0
#define xd_p_reg_cge_idx6_12_8	0xA28D
#define	reg_cge_idx6_12_8_pos 0
#define	reg_cge_idx6_12_8_len 5
#define	reg_cge_idx6_12_8_lsb 8
#define xd_p_reg_cge_idx7_7_0	0xA28E
#define	reg_cge_idx7_7_0_pos 0
#define	reg_cge_idx7_7_0_len 8
#define	reg_cge_idx7_7_0_lsb 0
#define xd_p_reg_cge_idx7_12_8	0xA28F
#define	reg_cge_idx7_12_8_pos 0
#define	reg_cge_idx7_12_8_len 5
#define	reg_cge_idx7_12_8_lsb 8
#define xd_p_reg_cge_idx8_7_0	0xA290
#define	reg_cge_idx8_7_0_pos 0
#define	reg_cge_idx8_7_0_len 8
#define	reg_cge_idx8_7_0_lsb 0
#define xd_p_reg_cge_idx8_12_8	0xA291
#define	reg_cge_idx8_12_8_pos 0
#define	reg_cge_idx8_12_8_len 5
#define	reg_cge_idx8_12_8_lsb 8
#define xd_p_reg_cge_idx9_7_0	0xA292
#define	reg_cge_idx9_7_0_pos 0
#define	reg_cge_idx9_7_0_len 8
#define	reg_cge_idx9_7_0_lsb 0
#define xd_p_reg_cge_idx9_12_8	0xA293
#define	reg_cge_idx9_12_8_pos 0
#define	reg_cge_idx9_12_8_len 5
#define	reg_cge_idx9_12_8_lsb 8
#define xd_p_reg_cge_idx10_7_0	0xA294
#define	reg_cge_idx10_7_0_pos 0
#define	reg_cge_idx10_7_0_len 8
#define	reg_cge_idx10_7_0_lsb 0
#define xd_p_reg_cge_idx10_12_8	0xA295
#define	reg_cge_idx10_12_8_pos 0
#define	reg_cge_idx10_12_8_len 5
#define	reg_cge_idx10_12_8_lsb 8
#define xd_p_reg_cge_idx11_7_0	0xA296
#define	reg_cge_idx11_7_0_pos 0
#define	reg_cge_idx11_7_0_len 8
#define	reg_cge_idx11_7_0_lsb 0
#define xd_p_reg_cge_idx11_12_8	0xA297
#define	reg_cge_idx11_12_8_pos 0
#define	reg_cge_idx11_12_8_len 5
#define	reg_cge_idx11_12_8_lsb 8
#define xd_p_reg_cge_idx12_7_0	0xA298
#define	reg_cge_idx12_7_0_pos 0
#define	reg_cge_idx12_7_0_len 8
#define	reg_cge_idx12_7_0_lsb 0
#define xd_p_reg_cge_idx12_12_8	0xA299
#define	reg_cge_idx12_12_8_pos 0
#define	reg_cge_idx12_12_8_len 5
#define	reg_cge_idx12_12_8_lsb 8
#define xd_p_reg_cge_idx13_7_0	0xA29A
#define	reg_cge_idx13_7_0_pos 0
#define	reg_cge_idx13_7_0_len 8
#define	reg_cge_idx13_7_0_lsb 0
#define xd_p_reg_cge_idx13_12_8	0xA29B
#define	reg_cge_idx13_12_8_pos 0
#define	reg_cge_idx13_12_8_len 5
#define	reg_cge_idx13_12_8_lsb 8
#define xd_p_reg_cge_idx14_7_0	0xA29C
#define	reg_cge_idx14_7_0_pos 0
#define	reg_cge_idx14_7_0_len 8
#define	reg_cge_idx14_7_0_lsb 0
#define xd_p_reg_cge_idx14_12_8	0xA29D
#define	reg_cge_idx14_12_8_pos 0
#define	reg_cge_idx14_12_8_len 5
#define	reg_cge_idx14_12_8_lsb 8
#define xd_p_reg_cge_idx15_7_0	0xA29E
#define	reg_cge_idx15_7_0_pos 0
#define	reg_cge_idx15_7_0_len 8
#define	reg_cge_idx15_7_0_lsb 0
#define xd_p_reg_cge_idx15_12_8	0xA29F
#define	reg_cge_idx15_12_8_pos 0
#define	reg_cge_idx15_12_8_len 5
#define	reg_cge_idx15_12_8_lsb 8
#define xd_r_reg_fft_crc	0xA2A8
#define	reg_fft_crc_pos 0
#define	reg_fft_crc_len 8
#define	reg_fft_crc_lsb 0
#define xd_p_fd_fft_shift_max	0xA2A9
#define	fd_fft_shift_max_pos 0
#define	fd_fft_shift_max_len 4
#define	fd_fft_shift_max_lsb 0
#define xd_r_fd_fft_shift	0xA2A9
#define	fd_fft_shift_pos 4
#define	fd_fft_shift_len 4
#define	fd_fft_shift_lsb 0
#define xd_r_fd_fft_frame_num	0xA2AA
#define	fd_fft_frame_num_pos 0
#define	fd_fft_frame_num_len 2
#define	fd_fft_frame_num_lsb 0
#define xd_r_fd_fft_symbol_count	0xA2AB
#define	fd_fft_symbol_count_pos 0
#define	fd_fft_symbol_count_len 7
#define	fd_fft_symbol_count_lsb 0
#define xd_r_reg_fft_idx_max_7_0	0xA2AC
#define	reg_fft_idx_max_7_0_pos 0
#define	reg_fft_idx_max_7_0_len 8
#define	reg_fft_idx_max_7_0_lsb 0
#define xd_r_reg_fft_idx_max_12_8	0xA2AD
#define	reg_fft_idx_max_12_8_pos 0
#define	reg_fft_idx_max_12_8_len 5
#define	reg_fft_idx_max_12_8_lsb 8
#define xd_p_reg_cge_program	0xA2AE
#define	reg_cge_program_pos 0
#define	reg_cge_program_len 1
#define	reg_cge_program_lsb 0
#define xd_p_reg_cge_fixed	0xA2AE
#define	reg_cge_fixed_pos 1
#define	reg_cge_fixed_len 1
#define	reg_cge_fixed_lsb 0
#define xd_p_reg_fft_rotate_en	0xA2AE
#define	reg_fft_rotate_en_pos 2
#define	reg_fft_rotate_en_len 1
#define	reg_fft_rotate_en_lsb 0
#define xd_p_reg_fft_rotate_base_4_0	0xA2AE
#define	reg_fft_rotate_base_4_0_pos 3
#define	reg_fft_rotate_base_4_0_len 5
#define	reg_fft_rotate_base_4_0_lsb 0
#define xd_p_reg_fft_rotate_base_12_5	0xA2AF
#define	reg_fft_rotate_base_12_5_pos 0
#define	reg_fft_rotate_base_12_5_len 8
#define	reg_fft_rotate_base_12_5_lsb 5
#define xd_p_reg_gp_trigger_fd	0xA2B8
#define	reg_gp_trigger_fd_pos 0
#define	reg_gp_trigger_fd_len 1
#define	reg_gp_trigger_fd_lsb 0
#define xd_p_reg_trigger_sel_fd	0xA2B8
#define	reg_trigger_sel_fd_pos 1
#define	reg_trigger_sel_fd_len 2
#define	reg_trigger_sel_fd_lsb 0
#define xd_p_reg_trigger_module_sel_fd	0xA2B9
#define	reg_trigger_module_sel_fd_pos 0
#define	reg_trigger_module_sel_fd_len 6
#