af9005.h

trident tm5600的linux驱动

#define xd_p_dagc1_accumulate_num_2k_12_8	0xA121
#define	dagc1_accumulate_num_2k_12_8_pos 0
#define	dagc1_accumulate_num_2k_12_8_len 5
#define	dagc1_accumulate_num_2k_12_8_lsb 8
#define xd_p_dagc1_accumulate_num_8k_7_0	0xA122
#define	dagc1_accumulate_num_8k_7_0_pos 0
#define	dagc1_accumulate_num_8k_7_0_len 8
#define	dagc1_accumulate_num_8k_7_0_lsb 0
#define xd_p_dagc1_accumulate_num_8k_14_8	0xA123
#define	dagc1_accumulate_num_8k_14_8_pos 0
#define	dagc1_accumulate_num_8k_14_8_len 7
#define	dagc1_accumulate_num_8k_14_8_lsb 8
#define xd_p_dagc1_desired_level_0	0xA123
#define	dagc1_desired_level_0_pos 7
#define	dagc1_desired_level_0_len 1
#define	dagc1_desired_level_0_lsb 0
#define xd_p_dagc1_desired_level_8_1	0xA124
#define	dagc1_desired_level_8_1_pos 0
#define	dagc1_desired_level_8_1_len 8
#define	dagc1_desired_level_8_1_lsb 1
#define xd_p_dagc1_apply_delay	0xA125
#define	dagc1_apply_delay_pos 0
#define	dagc1_apply_delay_len 7
#define	dagc1_apply_delay_lsb 0
#define xd_p_dagc1_bypass_scale_ctl	0xA126
#define	dagc1_bypass_scale_ctl_pos 0
#define	dagc1_bypass_scale_ctl_len 2
#define	dagc1_bypass_scale_ctl_lsb 0
#define xd_p_reg_dagc1_in_sat_cnt_7_0	0xA127
#define	reg_dagc1_in_sat_cnt_7_0_pos 0
#define	reg_dagc1_in_sat_cnt_7_0_len 8
#define	reg_dagc1_in_sat_cnt_7_0_lsb 0
#define xd_p_reg_dagc1_in_sat_cnt_15_8	0xA128
#define	reg_dagc1_in_sat_cnt_15_8_pos 0
#define	reg_dagc1_in_sat_cnt_15_8_len 8
#define	reg_dagc1_in_sat_cnt_15_8_lsb 8
#define xd_p_reg_dagc1_in_sat_cnt_23_16	0xA129
#define	reg_dagc1_in_sat_cnt_23_16_pos 0
#define	reg_dagc1_in_sat_cnt_23_16_len 8
#define	reg_dagc1_in_sat_cnt_23_16_lsb 16
#define xd_p_reg_dagc1_in_sat_cnt_31_24	0xA12A
#define	reg_dagc1_in_sat_cnt_31_24_pos 0
#define	reg_dagc1_in_sat_cnt_31_24_len 8
#define	reg_dagc1_in_sat_cnt_31_24_lsb 24
#define xd_p_reg_dagc1_out_sat_cnt_7_0	0xA12B
#define	reg_dagc1_out_sat_cnt_7_0_pos 0
#define	reg_dagc1_out_sat_cnt_7_0_len 8
#define	reg_dagc1_out_sat_cnt_7_0_lsb 0
#define xd_p_reg_dagc1_out_sat_cnt_15_8	0xA12C
#define	reg_dagc1_out_sat_cnt_15_8_pos 0
#define	reg_dagc1_out_sat_cnt_15_8_len 8
#define	reg_dagc1_out_sat_cnt_15_8_lsb 8
#define xd_p_reg_dagc1_out_sat_cnt_23_16	0xA12D
#define	reg_dagc1_out_sat_cnt_23_16_pos 0
#define	reg_dagc1_out_sat_cnt_23_16_len 8
#define	reg_dagc1_out_sat_cnt_23_16_lsb 16
#define xd_p_reg_dagc1_out_sat_cnt_31_24	0xA12E
#define	reg_dagc1_out_sat_cnt_31_24_pos 0
#define	reg_dagc1_out_sat_cnt_31_24_len 8
#define	reg_dagc1_out_sat_cnt_31_24_lsb 24
#define xd_r_dagc1_multiplier_7_0	0xA136
#define	dagc1_multiplier_7_0_pos 0
#define	dagc1_multiplier_7_0_len 8
#define	dagc1_multiplier_7_0_lsb 0
#define xd_r_dagc1_multiplier_15_8	0xA137
#define	dagc1_multiplier_15_8_pos 0
#define	dagc1_multiplier_15_8_len 8
#define	dagc1_multiplier_15_8_lsb 8
#define xd_r_dagc1_right_shift_bits	0xA138
#define	dagc1_right_shift_bits_pos 0
#define	dagc1_right_shift_bits_len 4
#define	dagc1_right_shift_bits_lsb 0
#define xd_p_reg_bfs_fcw_7_0	0xA140
#define	reg_bfs_fcw_7_0_pos 0
#define	reg_bfs_fcw_7_0_len 8
#define	reg_bfs_fcw_7_0_lsb 0
#define xd_p_reg_bfs_fcw_15_8	0xA141
#define	reg_bfs_fcw_15_8_pos 0
#define	reg_bfs_fcw_15_8_len 8
#define	reg_bfs_fcw_15_8_lsb 8
#define xd_p_reg_bfs_fcw_22_16	0xA142
#define	reg_bfs_fcw_22_16_pos 0
#define	reg_bfs_fcw_22_16_len 7
#define	reg_bfs_fcw_22_16_lsb 16
#define xd_p_reg_antif_sf_7_0	0xA144
#define	reg_antif_sf_7_0_pos 0
#define	reg_antif_sf_7_0_len 8
#define	reg_antif_sf_7_0_lsb 0
#define xd_p_reg_antif_sf_11_8	0xA145
#define	reg_antif_sf_11_8_pos 0
#define	reg_antif_sf_11_8_len 4
#define	reg_antif_sf_11_8_lsb 8
#define xd_r_bfs_fcw_q_7_0	0xA150
#define	bfs_fcw_q_7_0_pos 0
#define	bfs_fcw_q_7_0_len 8
#define	bfs_fcw_q_7_0_lsb 0
#define xd_r_bfs_fcw_q_15_8	0xA151
#define	bfs_fcw_q_15_8_pos 0
#define	bfs_fcw_q_15_8_len 8
#define	bfs_fcw_q_15_8_lsb 8
#define xd_r_bfs_fcw_q_22_16	0xA152
#define	bfs_fcw_q_22_16_pos 0
#define	bfs_fcw_q_22_16_len 7
#define	bfs_fcw_q_22_16_lsb 16
#define xd_p_reg_dca_enu	0xA160
#define	reg_dca_enu_pos 0
#define	reg_dca_enu_len 1
#define	reg_dca_enu_lsb 0
#define xd_p_reg_dca_enl	0xA160
#define	reg_dca_enl_pos 1
#define	reg_dca_enl_len 1
#define	reg_dca_enl_lsb 0
#define xd_p_reg_dca_lower_chip	0xA160
#define	reg_dca_lower_chip_pos 2
#define	reg_dca_lower_chip_len 1
#define	reg_dca_lower_chip_lsb 0
#define xd_p_reg_dca_upper_chip	0xA160
#define	reg_dca_upper_chip_pos 3
#define	reg_dca_upper_chip_len 1
#define	reg_dca_upper_chip_lsb 0
#define xd_p_reg_dca_platch	0xA160
#define	reg_dca_platch_pos 4
#define	reg_dca_platch_len 1
#define	reg_dca_platch_lsb 0
#define xd_p_reg_dca_th	0xA161
#define	reg_dca_th_pos 0
#define	reg_dca_th_len 5
#define	reg_dca_th_lsb 0
#define xd_p_reg_dca_scale	0xA162
#define	reg_dca_scale_pos 0
#define	reg_dca_scale_len 4
#define	reg_dca_scale_lsb 0
#define xd_p_reg_dca_tone_7_0	0xA163
#define	reg_dca_tone_7_0_pos 0
#define	reg_dca_tone_7_0_len 8
#define	reg_dca_tone_7_0_lsb 0
#define xd_p_reg_dca_tone_12_8	0xA164
#define	reg_dca_tone_12_8_pos 0
#define	reg_dca_tone_12_8_len 5
#define	reg_dca_tone_12_8_lsb 8
#define xd_p_reg_dca_time_7_0	0xA165
#define	reg_dca_time_7_0_pos 0
#define	reg_dca_time_7_0_len 8
#define	reg_dca_time_7_0_lsb 0
#define xd_p_reg_dca_time_15_8	0xA166
#define	reg_dca_time_15_8_pos 0
#define	reg_dca_time_15_8_len 8
#define	reg_dca_time_15_8_lsb 8
#define xd_r_dcasm	0xA167
#define	dcasm_pos 0
#define	dcasm_len 3
#define	dcasm_lsb 0
#define xd_p_reg_qnt_valuew_7_0	0xA168
#define	reg_qnt_valuew_7_0_pos 0
#define	reg_qnt_valuew_7_0_len 8
#define	reg_qnt_valuew_7_0_lsb 0
#define xd_p_reg_qnt_valuew_10_8	0xA169
#define	reg_qnt_valuew_10_8_pos 0
#define	reg_qnt_valuew_10_8_len 3
#define	reg_qnt_valuew_10_8_lsb 8
#define xd_p_dca_sbx_gain_diff_7_0	0xA16A
#define	dca_sbx_gain_diff_7_0_pos 0
#define	dca_sbx_gain_diff_7_0_len 8
#define	dca_sbx_gain_diff_7_0_lsb 0
#define xd_p_dca_sbx_gain_diff_9_8	0xA16B
#define	dca_sbx_gain_diff_9_8_pos 0
#define	dca_sbx_gain_diff_9_8_len 2
#define	dca_sbx_gain_diff_9_8_lsb 8
#define xd_p_reg_dca_stand_alone	0xA16C
#define	reg_dca_stand_alone_pos 0
#define	reg_dca_stand_alone_len 1
#define	reg_dca_stand_alone_lsb 0
#define xd_p_reg_dca_upper_out_en	0xA16C
#define	reg_dca_upper_out_en_pos 1
#define	reg_dca_upper_out_en_len 1
#define	reg_dca_upper_out_en_lsb 0
#define xd_p_reg_dca_rc_en	0xA16C
#define	reg_dca_rc_en_pos 2
#define	reg_dca_rc_en_len 1
#define	reg_dca_rc_en_lsb 0
#define xd_p_reg_dca_retrain_send	0xA16C
#define	reg_dca_retrain_send_pos 3
#define	reg_dca_retrain_send_len 1
#define	reg_dca_retrain_send_lsb 0
#define xd_p_reg_dca_retrain_rec	0xA16C
#define	reg_dca_retrain_rec_pos 4
#define	reg_dca_retrain_rec_len 1
#define	reg_dca_retrain_rec_lsb 0
#define xd_p_reg_dca_api_tpsrdy	0xA16C
#define	reg_dca_api_tpsrdy_pos 5
#define	reg_dca_api_tpsrdy_len 1
#define	reg_dca_api_tpsrdy_lsb 0
#define xd_p_reg_dca_symbol_gap	0xA16D
#define	reg_dca_symbol_gap_pos 0
#define	reg_dca_symbol_gap_len 4
#define	reg_dca_symbol_gap_lsb 0
#define xd_p_reg_qnt_nfvaluew_7_0	0xA16E
#define	reg_qnt_nfvaluew_7_0_pos 0
#define	reg_qnt_nfvaluew_7_0_len 8
#define	reg_qnt_nfvaluew_7_0_lsb 0
#define xd_p_reg_qnt_nfvaluew_10_8	0xA16F
#define	reg_qnt_nfvaluew_10_8_pos 0
#define	reg_qnt_nfvaluew_10_8_len 3
#define	reg_qnt_nfvaluew_10_8_lsb 8
#define xd_p_reg_qnt_flatness_thr_7_0	0xA170
#define	reg_qnt_flatness_thr_7_0_pos 0
#define	reg_qnt_flatness_thr_7_0_len 8
#define	reg_qnt_flatness_thr_7_0_lsb 0
#define xd_p_reg_qnt_flatness_thr_9_8	0xA171
#define	reg_qnt_flatness_thr_9_8_pos 0
#define	reg_qnt_flatness_thr_9_8_len 2
#define	reg_qnt_flatness_thr_9_8_lsb 8
#define xd_p_reg_dca_tone_idx_5_0	0xA171
#define	reg_dca_tone_idx_5_0_pos 2
#define	reg_dca_tone_idx_5_0_len 6
#define	reg_dca_tone_idx_5_0_lsb 0
#define xd_p_reg_dca_tone_idx_12_6	0xA172
#define	reg_dca_tone_idx_12_6_pos 0
#define	reg_dca_tone_idx_12_6_len 7
#define	reg_dca_tone_idx_12_6_lsb 6
#define xd_p_reg_dca_data_vld	0xA173
#define	reg_dca_data_vld_pos 0
#define	reg_dca_data_vld_len 1
#define	reg_dca_data_vld_lsb 0
#define xd_p_reg_dca_read_update	0xA173
#define	reg_dca_read_update_pos 1
#define	reg_dca_read_update_len 1
#define	reg_dca_read_update_lsb 0
#define xd_r_reg_dca_data_re_5_0	0xA173
#define	reg_dca_data_re_5_0_pos 2
#define	reg_dca_data_re_5_0_len 6
#define	reg_dca_data_re_5_0_lsb 0
#define xd_r_reg_dca_data_re_10_6	0xA174
#define	reg_dca_data_re_10_6_pos 0
#define	reg_dca_data_re_10_6_len 5
#define	reg_dca_data_re_10_6_lsb 6
#define xd_r_reg_dca_data_im_7_0	0xA175
#define	reg_dca_data_im_7_0_pos 0
#define	reg_dca_data_im_7_0_len 8
#define	reg_dca_data_im_7_0_lsb 0
#define xd_r_reg_dca_data_im_10_8	0xA176
#define	reg_dca_data_im_10_8_pos 0
#define	reg_dca_data_im_10_8_len 3
#define	reg_dca_data_im_10_8_lsb 8
#define xd_r_reg_dca_data_h2_7_0	0xA178
#define	reg_dca_data_h2_7_0_pos 0
#define	reg_dca_data_h2_7_0_len 8
#define	reg_dca_data_h2_7_0_lsb 0
#define xd_r_reg_dca_data_h2_9_8	0xA179
#define	reg_dca_data_h2_9_8_pos 0
#define	reg_dca_data_h2_9_8_len 2
#define	reg_dca_data_h2_9_8_lsb 8
#define xd_p_reg_f_adc_7_0	0xA180
#define	reg_f_adc_7_0_pos 0
#define	reg_f_adc_7_0_len 8
#define	reg_f_adc_7_0_lsb 0
#define xd_p_reg_f_adc_15_8	0xA181
#define	reg_f_adc_15_8_pos 0
#define	reg_f_adc_15_8_len 8
#define	reg_f_adc_15_8_lsb 8
#define xd_p_reg_f_adc_23_16	0xA182
#define	reg_f_adc_23_16_pos 0
#define	reg_f_adc_23_16_len 8
#define	reg_f_adc_23_16_lsb 16
#define xd_r_intp_mu_7_0	0xA190
#define	intp_mu_7_0_pos 0
#define	intp_mu_7_0_len 8
#define	intp_mu_7_0_lsb 0
#define xd_r_intp_mu_15_8	0xA191
#define	intp_mu_15_8_pos 0
#define	intp_mu_15_8_len 8
#define	intp_mu_15_8_lsb 8
#define xd_r_intp_mu_19_16	0xA192
#define	intp_mu_19_16_pos 0
#define	intp_mu_19_16_len 4
#define	intp_mu_19_16_lsb 16
#define xd_p_reg_agc_rst	0xA1A0
#define	reg_agc_rst_pos 0
#define	reg_agc_rst_len 1
#define	reg_agc_rst_lsb 0
#define xd_p_rf_agc_en	0xA1A0
#define	rf_agc_en_pos 1
#define	rf_agc_en_len 1
#define	rf_agc_en_lsb 0
#define xd_p_rf_agc_dis	0xA1A0
#define	rf_agc_dis_pos 2
#define	rf_agc_dis_len 1
#define	rf_agc_dis_lsb 0
#define xd_p_if_agc_rst	0xA1A0
#define	if_agc_rst_pos 3
#define	if_agc_rst_len 1
#define	if_agc_rst_lsb 0
#define xd_p_if_agc_en	0xA1A0
#define	if_agc_en_pos 4
#define	if_agc_en_len 1
#define	if_agc_en_lsb 0
#define xd_p_if_agc_dis	0xA1A0
#define	if_agc_dis_pos 5
#define	if_agc_dis_len 1
#define	if_agc_dis_lsb 0
#define xd_p_agc_lock	0xA1A0
#define	agc_lock_pos 6
#define	agc_lock_len 1
#define	agc_lock_lsb 0
#define xd_p_reg_tinr_rst	0xA1A1
#define	reg_tinr_rst_pos 0
#define	reg_tinr_rst_len 1
#define	reg_tinr_rst_lsb 0
#define xd_p_reg_tinr_en	0xA1A1
#define	reg_tinr_en_pos 1
#define	reg_tinr_en_len 1
#define	reg_tinr_en_lsb 0
#define xd_p_reg_ccifs_en	0xA1A2
#define	reg_ccifs_en_pos 0
#define	reg_ccifs_en_len 1
#define	reg_ccifs_en_lsb 0
#define xd_p_reg_ccifs_dis	0xA1A2
#define	reg_ccifs_dis_pos 1
#define	reg_ccifs_dis_len 1
#define	reg_ccifs_dis_lsb 0
#define xd_p_reg_ccifs_rst	0xA1A2
#define	reg_ccifs_rst_pos 2
#define	reg_ccifs_rst_len 1
#define	reg_ccifs_rst_lsb 0
#define xd_p_reg_ccifs_byp	0xA1A2
#define	reg_ccifs_byp_pos 3
#define	reg_ccifs_byp_len 1
#define	reg_ccifs_byp_lsb 0
#define xd_p_reg_ccif_en	0xA1A3
#define	reg_ccif_en_pos 0
#define	reg_ccif_en_len 1
#define	reg_ccif_en_lsb 0
#define xd_p_reg_ccif_dis	0xA1A3
#define	reg_ccif_dis_pos 1
#define	reg_ccif_dis_len 1
#define	reg_ccif_dis_lsb 0
#define xd_p_reg_ccif_rst	0xA1A3
#define	reg_ccif_rst_pos 2
#define	reg_ccif_rst_len 1
#define	reg_ccif_rst_lsb 0
#define xd_p_reg_ccif_byp	0xA1A3
#define	reg_ccif_byp_pos 3
#define	reg_ccif_byp_len 1
#define	reg_ccif_byp_lsb 0
#define xd_p_dagc1_rst	0xA1A4
#define	dagc1_rst_pos 0
#define	dagc1_rst_len 1
#define	dagc1_rst_lsb 0
#define xd_p_dagc1_en	0xA1A4
#define	dagc1_en_pos 1
#define	dagc1_en_len 1
#define	dagc1_en_lsb 0
#define xd_p_dagc1_mode	0xA1A4
#define	dagc1_mode_pos 2
#define	dagc1_mode_len 2
#define	dagc1_mode_lsb 0
#define xd_p_dagc1_done	0xA1A4
#define	dagc1_done_pos 4
#define	dagc1_done_len 1
#define	dagc1_done_lsb 0
#define xd_p_ccid_rst	0xA1A5
#define	ccid_rst_pos 0
#define	ccid_rst_len 1
#define	ccid_rst_lsb 0
#define xd_p_ccid_en	0xA1A5
#define	ccid_en_pos 1
#define	ccid_en_len 1
#define	ccid_en_lsb 0
#define xd_p_ccid_mode	0xA1A5
#define	ccid_mode_pos 2
#define	ccid_mode_len 2
#define	ccid_mode_lsb 0