📄 stm8s_tim1.ls
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3745 0454 a48f and a,#143
3746 0456 1a01 or a,(OFST+1,sp)
3747 0458 c75258 ld 21080,a
3748 ; 1374 }
3751 045b 84 pop a
3752 045c 81 ret
3788 ; 1395 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3788 ; 1396 {
3789 switch .text
3790 045d _TIM1_ForcedOC2Config:
3792 045d 88 push a
3793 00000000 OFST: set 0
3796 ; 1398 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3798 ; 1401 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3800 045e c65259 ld a,21081
3801 0461 a48f and a,#143
3802 0463 1a01 or a,(OFST+1,sp)
3803 0465 c75259 ld 21081,a
3804 ; 1402 }
3807 0468 84 pop a
3808 0469 81 ret
3844 ; 1423 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3844 ; 1424 {
3845 switch .text
3846 046a _TIM1_ForcedOC3Config:
3848 046a 88 push a
3849 00000000 OFST: set 0
3852 ; 1426 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3854 ; 1429 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3856 046b c6525a ld a,21082
3857 046e a48f and a,#143
3858 0470 1a01 or a,(OFST+1,sp)
3859 0472 c7525a ld 21082,a
3860 ; 1430 }
3863 0475 84 pop a
3864 0476 81 ret
3900 ; 1451 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3900 ; 1452 {
3901 switch .text
3902 0477 _TIM1_ForcedOC4Config:
3904 0477 88 push a
3905 00000000 OFST: set 0
3908 ; 1454 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3910 ; 1457 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3912 0478 c6525b ld a,21083
3913 047b a48f and a,#143
3914 047d 1a01 or a,(OFST+1,sp)
3915 047f c7525b ld 21083,a
3916 ; 1458 }
3919 0482 84 pop a
3920 0483 81 ret
3956 ; 1476 void TIM1_ARRPreloadConfig(FunctionalState NewState)
3956 ; 1477 {
3957 switch .text
3958 0484 _TIM1_ARRPreloadConfig:
3962 ; 1479 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3964 ; 1482 if (NewState != DISABLE)
3966 0484 4d tnz a
3967 0485 2705 jreq L1502
3968 ; 1484 TIM1->CR1 |= TIM1_CR1_ARPE;
3970 0487 721e5250 bset 21072,#7
3973 048b 81 ret
3974 048c L1502:
3975 ; 1488 TIM1->CR1 &= (u8)(~TIM1_CR1_ARPE);
3977 048c 721f5250 bres 21072,#7
3978 ; 1490 }
3981 0490 81 ret
4016 ; 1508 void TIM1_SelectCOM(FunctionalState NewState)
4016 ; 1509 {
4017 switch .text
4018 0491 _TIM1_SelectCOM:
4022 ; 1511 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4024 ; 1514 if (NewState != DISABLE)
4026 0491 4d tnz a
4027 0492 2705 jreq L3702
4028 ; 1516 TIM1->CR2 |= TIM1_CR2_COMS;
4030 0494 72145251 bset 21073,#2
4033 0498 81 ret
4034 0499 L3702:
4035 ; 1520 TIM1->CR2 &= (u8)(~TIM1_CR2_COMS);
4037 0499 72155251 bres 21073,#2
4038 ; 1522 }
4041 049d 81 ret
4077 ; 1539 void TIM1_CCPreloadControl(FunctionalState NewState)
4077 ; 1540 {
4078 switch .text
4079 049e _TIM1_CCPreloadControl:
4083 ; 1542 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4085 ; 1545 if (NewState != DISABLE)
4087 049e 4d tnz a
4088 049f 2705 jreq L5112
4089 ; 1547 TIM1->CR2 |= TIM1_CR2_CCPC;
4091 04a1 72105251 bset 21073,#0
4094 04a5 81 ret
4095 04a6 L5112:
4096 ; 1551 TIM1->CR2 &= (u8)(~TIM1_CR2_CCPC);
4098 04a6 72115251 bres 21073,#0
4099 ; 1553 }
4102 04aa 81 ret
4138 ; 1571 void TIM1_OC1PreloadConfig(FunctionalState NewState)
4138 ; 1572 {
4139 switch .text
4140 04ab _TIM1_OC1PreloadConfig:
4144 ; 1574 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4146 ; 1577 if (NewState != DISABLE)
4148 04ab 4d tnz a
4149 04ac 2705 jreq L7312
4150 ; 1579 TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
4152 04ae 72165258 bset 21080,#3
4155 04b2 81 ret
4156 04b3 L7312:
4157 ; 1583 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxPE);
4159 04b3 72175258 bres 21080,#3
4160 ; 1585 }
4163 04b7 81 ret
4199 ; 1603 void TIM1_OC2PreloadConfig(FunctionalState NewState)
4199 ; 1604 {
4200 switch .text
4201 04b8 _TIM1_OC2PreloadConfig:
4205 ; 1606 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4207 ; 1609 if (NewState != DISABLE)
4209 04b8 4d tnz a
4210 04b9 2705 jreq L1612
4211 ; 1611 TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
4213 04bb 72165259 bset 21081,#3
4216 04bf 81 ret
4217 04c0 L1612:
4218 ; 1615 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxPE);
4220 04c0 72175259 bres 21081,#3
4221 ; 1617 }
4224 04c4 81 ret
4260 ; 1635 void TIM1_OC3PreloadConfig(FunctionalState NewState)
4260 ; 1636 {
4261 switch .text
4262 04c5 _TIM1_OC3PreloadConfig:
4266 ; 1638 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4268 ; 1641 if (NewState != DISABLE)
4270 04c5 4d tnz a
4271 04c6 2705 jreq L3022
4272 ; 1643 TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
4274 04c8 7216525a bset 21082,#3
4277 04cc 81 ret
4278 04cd L3022:
4279 ; 1647 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxPE);
4281 04cd 7217525a bres 21082,#3
4282 ; 1649 }
4285 04d1 81 ret
4321 ; 1668 void TIM1_OC4PreloadConfig(FunctionalState NewState)
4321 ; 1669 {
4322 switch .text
4323 04d2 _TIM1_OC4PreloadConfig:
4327 ; 1671 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4329 ; 1674 if (NewState != DISABLE)
4331 04d2 4d tnz a
4332 04d3 2705 jreq L5222
4333 ; 1676 TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
4335 04d5 7216525b bset 21083,#3
4338 04d9 81 ret
4339 04da L5222:
4340 ; 1680 TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxPE);
4342 04da 7217525b bres 21083,#3
4343 ; 1682 }
4346 04de 81 ret
4381 ; 1699 void TIM1_OC1FastConfig(FunctionalState NewState)
4381 ; 1700 {
4382 switch .text
4383 04df _TIM1_OC1FastConfig:
4387 ; 1702 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4389 ; 1705 if (NewState != DISABLE)
4391 04df 4d tnz a
4392 04e0 2705 jreq L7422
4393 ; 1707 TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
4395 04e2 72145258 bset 21080,#2
4398 04e6 81 ret
4399 04e7 L7422:
4400 ; 1711 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxFE);
4402 04e7 72155258 bres 21080,#2
4403 ; 1713 }
4406 04eb 81 ret
4441 ; 1732 void TIM1_OC2FastConfig(FunctionalState NewState)
4441 ; 1733 {
4442 switch .text
4443 04ec _TIM1_OC2FastConfig:
4447 ; 1735 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4449 ; 1738 if (NewState != DISABLE)
4451 04ec 4d tnz a
4452 04ed 2705 jreq L1722
4453 ; 1740 TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
4455 04ef 72145259 bset 21081,#2
4458 04f3 81 ret
4459 04f4 L1722:
4460 ; 1744 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxFE);
4462 04f4 72155259 bres 21081,#2
4463 ; 1746 }
4466 04f8 81 ret
4501 ; 1764 void TIM1_OC3FastConfig(FunctionalState NewState)
4501 ; 1765 {
4502 switch .text
4503 04f9 _TIM1_OC3FastConfig:
4507 ; 1767 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4509 ; 1770 if (NewState != DISABLE)
4511 04f9 4d tnz a
4512 04fa 2705 jreq L3132
4513 ; 1772 TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
4515 04fc 7214525a bset 21082,#2
4518 0500 81 ret
4519 0501 L3132:
4520 ; 1776 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxFE);
4522 0501 7215525a bres 21082,#2
4523 ; 1778 }
4526 0505 81 ret
4561 ; 1796 void TIM1_OC4FastConfig(FunctionalState NewState)
4561 ; 1797 {
4562 switch .text
4563 0506 _TIM1_OC4FastConfig:
4567 ; 1799 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4569 ; 1802 if (NewState != DISABLE)
4571 0506 4d tnz a
4572 0507 2705 jreq L5332
4573 ; 1804 TIM1->CCMR4 |= TIM1_CCMR_OCxFE;
4575 0509 7214525b bset 21083,#2
4578 050d 81 ret
4579 050e L5332:
4580 ; 1808 TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxFE);
4582 050e 7215525b bres 21083,#2
4583 ; 1810 }
4586 0512 81 ret
4691 ; 1836 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource)
4691 ; 1837 {
4692 switch .text
4693 0513 _TIM1_GenerateEvent:
4697 ; 1839 assert_param(IS_TIM1_EVENT_SOURCE_OK(TIM1_EventSource));
4699 ; 1842 TIM1->EGR = (u8)TIM1_EventSource;
4701 0513 c75257 ld 21079,a
4702 ; 1843 }
4705 0516 81 ret
4741 ; 1863 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
4741 ; 1864 {
4742 switch .text
4743 0517 _TIM1_OC1PolarityConfig:
4747 ; 1866 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
4749 ; 1869 if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
4751 0517 4d tnz a
4752 0518 2705 jreq L1242
4753 ; 1871 TIM1->CCER1 |= TIM1_CCER1_CC1P;
4755 051a 7212525c bset 21084,#1
4758 051e 81 ret
4759 051f L1242:
4760 ; 1875 ⌨️ 快捷键说明
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