📄 stm8s_tim1.ls
字号:
2684 0361 a160 cp a,#96
2685 0363 260e jrne L1131
2686 ; 946 TI2_Config(TIM1_ICPolarity, TIM1_ICSELECTION_DIRECTTI, ICFilter);
2688 0365 7b05 ld a,(OFST+5,sp)
2689 0367 88 push a
2690 0368 ae0001 ldw x,#1
2691 036b 7b03 ld a,(OFST+3,sp)
2692 036d 95 ld xh,a
2693 036e cd07d7 call L5_TI2_Config
2696 0371 200c jra L3131
2697 0373 L1131:
2698 ; 950 TI1_Config(TIM1_ICPolarity, TIM1_ICSELECTION_DIRECTTI, ICFilter);
2700 0373 7b05 ld a,(OFST+5,sp)
2701 0375 88 push a
2702 0376 ae0001 ldw x,#1
2703 0379 7b03 ld a,(OFST+3,sp)
2704 037b 95 ld xh,a
2705 037c cd07a7 call L3_TI1_Config
2707 037f L3131:
2708 037f 84 pop a
2709 ; 954 TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
2711 0380 7b01 ld a,(OFST+1,sp)
2712 0382 ad0a call _TIM1_SelectInputTrigger
2714 ; 957 TIM1->SMCR |= (u8)(TIM1_SLAVEMODE_EXTERNAL1);
2716 0384 c65252 ld a,21074
2717 0387 aa07 or a,#7
2718 0389 c75252 ld 21074,a
2719 ; 958 }
2722 038c 85 popw x
2723 038d 81 ret
2794 ; 979 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
2794 ; 980 {
2795 switch .text
2796 038e _TIM1_SelectInputTrigger:
2798 038e 88 push a
2799 00000000 OFST: set 0
2802 ; 982 assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));
2804 ; 985 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_TS)) | (u8)TIM1_InputTriggerSource);
2806 038f c65252 ld a,21074
2807 0392 a48f and a,#143
2808 0394 1a01 or a,(OFST+1,sp)
2809 0396 c75252 ld 21074,a
2810 ; 986 }
2813 0399 84 pop a
2814 039a 81 ret
2850 ; 1005 void TIM1_UpdateDisableConfig(FunctionalState NewState)
2850 ; 1006 {
2851 switch .text
2852 039b _TIM1_UpdateDisableConfig:
2856 ; 1008 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2858 ; 1011 if (NewState != DISABLE)
2860 039b 4d tnz a
2861 039c 2705 jreq L5631
2862 ; 1013 TIM1->CR1 |= TIM1_CR1_UDIS;
2864 039e 72125250 bset 21072,#1
2867 03a2 81 ret
2868 03a3 L5631:
2869 ; 1017 TIM1->CR1 &= (u8)(~TIM1_CR1_UDIS);
2871 03a3 72135250 bres 21072,#1
2872 ; 1019 }
2875 03a7 81 ret
2933 ; 1038 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
2933 ; 1039 {
2934 switch .text
2935 03a8 _TIM1_UpdateRequestConfig:
2939 ; 1041 assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));
2941 ; 1044 if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
2943 03a8 4d tnz a
2944 03a9 2705 jreq L7141
2945 ; 1046 TIM1->CR1 |= TIM1_CR1_URS;
2947 03ab 72145250 bset 21072,#2
2950 03af 81 ret
2951 03b0 L7141:
2952 ; 1050 TIM1->CR1 &= (u8)(~TIM1_CR1_URS);
2954 03b0 72155250 bres 21072,#2
2955 ; 1052 }
2958 03b4 81 ret
2994 ; 1070 void TIM1_SelectHallSensor(FunctionalState NewState)
2994 ; 1071 {
2995 switch .text
2996 03b5 _TIM1_SelectHallSensor:
3000 ; 1073 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3002 ; 1076 if (NewState != DISABLE)
3004 03b5 4d tnz a
3005 03b6 2705 jreq L1441
3006 ; 1078 TIM1->CR2 |= TIM1_CR2_TI1S;
3008 03b8 721e5251 bset 21073,#7
3011 03bc 81 ret
3012 03bd L1441:
3013 ; 1082 TIM1->CR2 &= (u8)(~TIM1_CR2_TI1S);
3015 03bd 721f5251 bres 21073,#7
3016 ; 1084 }
3019 03c1 81 ret
3076 ; 1104 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
3076 ; 1105 {
3077 switch .text
3078 03c2 _TIM1_SelectOnePulseMode:
3082 ; 1107 assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));
3084 ; 1110 if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
3086 03c2 4d tnz a
3087 03c3 2705 jreq L3741
3088 ; 1112 TIM1->CR1 |= TIM1_CR1_OPM;
3090 03c5 72165250 bset 21072,#3
3093 03c9 81 ret
3094 03ca L3741:
3095 ; 1116 TIM1->CR1 &= (u8)(~TIM1_CR1_OPM);
3097 03ca 72175250 bres 21072,#3
3098 ; 1119 }
3101 03ce 81 ret
3199 ; 1144 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
3199 ; 1145 {
3200 switch .text
3201 03cf _TIM1_SelectOutputTrigger:
3203 03cf 88 push a
3204 00000000 OFST: set 0
3207 ; 1148 assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
3209 ; 1150 TIM1->CR2 = (u8)((TIM1->CR2 & (u8)(~TIM1_CR2_MMS )) | (u8) TIM1_TRGOSource);
3211 03d0 c65251 ld a,21073
3212 03d3 a48f and a,#143
3213 03d5 1a01 or a,(OFST+1,sp)
3214 03d7 c75251 ld 21073,a
3215 ; 1151 }
3218 03da 84 pop a
3219 03db 81 ret
3293 ; 1172 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
3293 ; 1173 {
3294 switch .text
3295 03dc _TIM1_SelectSlaveMode:
3297 03dc 88 push a
3298 00000000 OFST: set 0
3301 ; 1176 assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));
3303 ; 1179 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_SMS)) | (u8)TIM1_SlaveMode);
3305 03dd c65252 ld a,21074
3306 03e0 a4f8 and a,#248
3307 03e2 1a01 or a,(OFST+1,sp)
3308 03e4 c75252 ld 21074,a
3309 ; 1181 }
3312 03e7 84 pop a
3313 03e8 81 ret
3349 ; 1198 void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
3349 ; 1199 {
3350 switch .text
3351 03e9 _TIM1_SelectMasterSlaveMode:
3355 ; 1201 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3357 ; 1204 if (NewState != DISABLE)
3359 03e9 4d tnz a
3360 03ea 2705 jreq L7061
3361 ; 1206 TIM1->SMCR |= TIM1_SMCR_MSM;
3363 03ec 721e5252 bset 21074,#7
3366 03f0 81 ret
3367 03f1 L7061:
3368 ; 1210 TIM1->SMCR &= (u8)(~TIM1_SMCR_MSM);
3370 03f1 721f5252 bres 21074,#7
3371 ; 1212 }
3374 03f5 81 ret
3460 ; 1243 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
3460 ; 1244 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
3460 ; 1245 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
3460 ; 1246 {
3461 switch .text
3462 03f6 _TIM1_EncoderInterfaceConfig:
3464 03f6 89 pushw x
3465 00000000 OFST: set 0
3468 ; 1250 assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
3470 ; 1251 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
3472 ; 1252 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));
3474 ; 1255 if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
3476 03f7 9f ld a,xl
3477 03f8 4d tnz a
3478 03f9 2706 jreq L3561
3479 ; 1257 TIM1->CCER1 |= TIM1_CCER1_CC1P;
3481 03fb 7212525c bset 21084,#1
3483 03ff 2004 jra L5561
3484 0401 L3561:
3485 ; 1261 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P);
3487 0401 7213525c bres 21084,#1
3488 0405 L5561:
3489 ; 1264 if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
3491 0405 7b05 ld a,(OFST+5,sp)
3492 0407 2706 jreq L7561
3493 ; 1266 TIM1->CCER1 |= TIM1_CCER1_CC2P;
3495 0409 721a525c bset 21084,#5
3497 040d 2004 jra L1661
3498 040f L7561:
3499 ; 1270 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P);
3501 040f 721b525c bres 21084,#5
3502 0413 L1661:
3503 ; 1273 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (u8) TIM1_EncoderMode);
3505 0413 c65252 ld a,21074
3506 0416 a4f0 and a,#240
3507 0418 1a01 or a,(OFST+1,sp)
3508 041a c75252 ld 21074,a
3509 ; 1276 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3511 041d c65258 ld a,21080
3512 0420 a4fc and a,#252
3513 0422 aa01 or a,#1
3514 0424 c75258 ld 21080,a
3515 ; 1277 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3517 0427 c65259 ld a,21081
3518 042a a4fc and a,#252
3519 042c aa01 or a,#1
3520 042e c75259 ld 21081,a
3521 ; 1279 }
3524 0431 85 popw x
3525 0432 81 ret
3592 ; 1303 void TIM1_PrescalerConfig(u16 Prescaler,
3592 ; 1304 TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
3592 ; 1305 {
3593 switch .text
3594 0433 _TIM1_PrescalerConfig:
3596 0433 89 pushw x
3597 00000000 OFST: set 0
3600 ; 1307 assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));
3602 ; 1310 TIM1->PSCRH = (u8)(Prescaler >> 8);
3604 0434 9e ld a,xh
3605 0435 c75260 ld 21088,a
3606 ; 1311 TIM1->PSCRL = (u8)(Prescaler);
3608 0438 9f ld a,xl
3609 0439 c75261 ld 21089,a
3610 ; 1314 TIM1->EGR = TIM1_PSCReloadMode;
3612 043c 7b05 ld a,(OFST+5,sp)
3613 043e c75257 ld 21079,a
3614 ; 1316 }
3617 0441 85 popw x
3618 0442 81 ret
3654 ; 1338 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
3654 ; 1339 {
3655 switch .text
3656 0443 _TIM1_CounterModeConfig:
3658 0443 88 push a
3659 00000000 OFST: set 0
3662 ; 1341 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
3664 ; 1345 TIM1->CR1 = (u8)((TIM1->CR1 & (u8)((u8)(~TIM1_CR1_CMS) & (u8)(~TIM1_CR1_DIR))) | (u8)TIM1_CounterMode);
3666 0444 c65250 ld a,21072
3667 0447 a48f and a,#143
3668 0449 1a01 or a,(OFST+1,sp)
3669 044b c75250 ld 21072,a
3670 ; 1346 }
3673 044e 84 pop a
3674 044f 81 ret
3732 ; 1367 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3732 ; 1368 {
3733 switch .text
3734 0450 _TIM1_ForcedOC1Config:
3736 0450 88 push a
3737 00000000 OFST: set 0
3740 ; 1370 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3742 ; 1373 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3744 0451 c65258 ld a,21080
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