📄 stm8s_tim1.ls
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844 016c c75267 ld 21095,a
845 ; 290 TIM1->CCR2L = (u8)(TIM1_Pulse);
847 016f 7b0a ld a,(OFST+7,sp)
848 0171 c75268 ld 21096,a
849 ; 292 }
852 0174 5b05 addw sp,#5
853 0176 81 ret
957 ; 323 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
957 ; 324 TIM1_OutputState_TypeDef TIM1_OutputState,
957 ; 325 TIM1_OutputNState_TypeDef TIM1_OutputNState,
957 ; 326 u16 TIM1_Pulse,
957 ; 327 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
957 ; 328 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
957 ; 329 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
957 ; 330 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
957 ; 331 {
958 switch .text
959 0177 _TIM1_OC3Init:
961 0177 89 pushw x
962 0178 5203 subw sp,#3
963 00000003 OFST: set 3
966 ; 334 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
968 ; 335 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
970 ; 336 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
972 ; 337 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
974 ; 338 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
976 ; 339 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
978 ; 340 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
980 ; 343 TIM1->CCER2 &= (u8)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
982 017a c6525d ld a,21085
983 017d a4f0 and a,#240
984 017f c7525d ld 21085,a
985 ; 345 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC3E ) | (TIM1_OutputNState & TIM1_CCER2_CC3NE ) | (TIM1_OCPolarity & TIM1_CCER2_CC3P ) | (TIM1_OCNPolarity & TIM1_CCER2_CC3NP ));
987 0182 7b0c ld a,(OFST+9,sp)
988 0184 a408 and a,#8
989 0186 6b03 ld (OFST+0,sp),a
990 0188 7b0b ld a,(OFST+8,sp)
991 018a a402 and a,#2
992 018c 6b02 ld (OFST-1,sp),a
993 018e 7b08 ld a,(OFST+5,sp)
994 0190 a404 and a,#4
995 0192 6b01 ld (OFST-2,sp),a
996 0194 9f ld a,xl
997 0195 a401 and a,#1
998 0197 1a01 or a,(OFST-2,sp)
999 0199 1a02 or a,(OFST-1,sp)
1000 019b 1a03 or a,(OFST+0,sp)
1001 019d ca525d or a,21085
1002 01a0 c7525d ld 21085,a
1003 ; 350 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
1005 01a3 c6525a ld a,21082
1006 01a6 a48f and a,#143
1007 01a8 1a04 or a,(OFST+1,sp)
1008 01aa c7525a ld 21082,a
1009 ; 353 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
1011 01ad c6526f ld a,21103
1012 01b0 a4cf and a,#207
1013 01b2 c7526f ld 21103,a
1014 ; 355 TIM1->OISR |= (u8)((TIM1_OISR_OIS3 & TIM1_OCIdleState) | (TIM1_OISR_OIS3N & TIM1_OCNIdleState));
1016 01b5 7b0e ld a,(OFST+11,sp)
1017 01b7 a420 and a,#32
1018 01b9 6b03 ld (OFST+0,sp),a
1019 01bb 7b0d ld a,(OFST+10,sp)
1020 01bd a410 and a,#16
1021 01bf 1a03 or a,(OFST+0,sp)
1022 01c1 ca526f or a,21103
1023 01c4 c7526f ld 21103,a
1024 ; 358 TIM1->CCR3H = (u8)(TIM1_Pulse >> 8);
1026 01c7 7b09 ld a,(OFST+6,sp)
1027 01c9 c75269 ld 21097,a
1028 ; 359 TIM1->CCR3L = (u8)(TIM1_Pulse);
1030 01cc 7b0a ld a,(OFST+7,sp)
1031 01ce c7526a ld 21098,a
1032 ; 361 }
1035 01d1 5b05 addw sp,#5
1036 01d3 81 ret
1110 ; 386 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
1110 ; 387 TIM1_OutputState_TypeDef TIM1_OutputState,
1110 ; 388 u16 TIM1_Pulse,
1110 ; 389 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
1110 ; 390 TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
1110 ; 391 {
1111 switch .text
1112 01d4 _TIM1_OC4Init:
1114 01d4 89 pushw x
1115 01d5 88 push a
1116 00000001 OFST: set 1
1119 ; 394 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
1121 ; 395 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
1123 ; 396 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
1125 ; 397 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
1127 ; 402 TIM1->CCER2 &= (u8)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));
1129 01d6 c6525d ld a,21085
1130 01d9 a4cf and a,#207
1131 01db c7525d ld 21085,a
1132 ; 404 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC4E ) | (TIM1_OCPolarity & TIM1_CCER2_CC4P ));
1134 01de 7b08 ld a,(OFST+7,sp)
1135 01e0 a420 and a,#32
1136 01e2 6b01 ld (OFST+0,sp),a
1137 01e4 9f ld a,xl
1138 01e5 a410 and a,#16
1139 01e7 1a01 or a,(OFST+0,sp)
1140 01e9 ca525d or a,21085
1141 01ec c7525d ld 21085,a
1142 ; 407 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (TIM1_OCMode));
1144 01ef c6525b ld a,21083
1145 01f2 a48f and a,#143
1146 01f4 1a02 or a,(OFST+1,sp)
1147 01f6 c7525b ld 21083,a
1148 ; 410 if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)
1150 01f9 7b09 ld a,(OFST+8,sp)
1151 01fb 270a jreq L534
1152 ; 412 TIM1->OISR |= (u8)(~TIM1_CCER2_CC4P);
1154 01fd c6526f ld a,21103
1155 0200 aadf or a,#223
1156 0202 c7526f ld 21103,a
1158 0205 2004 jra L734
1159 0207 L534:
1160 ; 416 TIM1->OISR &= (u8)(~TIM1_OISR_OIS4);
1162 0207 721d526f bres 21103,#6
1163 020b L734:
1164 ; 420 TIM1->CCR4H = (u8)(TIM1_Pulse >> 8);
1166 020b 7b06 ld a,(OFST+5,sp)
1167 020d c7526b ld 21099,a
1168 ; 421 TIM1->CCR4L = (u8)(TIM1_Pulse);
1170 0210 7b07 ld a,(OFST+6,sp)
1171 0212 c7526c ld 21100,a
1172 ; 423 }
1175 0215 5b03 addw sp,#3
1176 0217 81 ret
1381 ; 451 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
1381 ; 452 TIM1_LockLevel_TypeDef TIM1_LockLevel,
1381 ; 453 u8 TIM1_DeadTime,
1381 ; 454 TIM1_BreakState_TypeDef TIM1_Break,
1381 ; 455 TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
1381 ; 456 TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
1381 ; 457 {
1382 switch .text
1383 0218 _TIM1_BDTRConfig:
1385 0218 89 pushw x
1386 00000000 OFST: set 0
1389 ; 461 assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));
1391 ; 462 assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));
1393 ; 463 assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));
1395 ; 464 assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));
1397 ; 465 assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));
1399 ; 468 TIM1->DTR = (u8)(TIM1_DeadTime);
1401 0219 7b05 ld a,(OFST+5,sp)
1402 021b c7526e ld 21102,a
1403 ; 472 TIM1->BKR = (u8)((u8)TIM1_OSSIState | \
1403 ; 473 (u8)TIM1_LockLevel | \
1403 ; 474 (u8)TIM1_Break | \
1403 ; 475 (u8)TIM1_BreakPolarity | \
1403 ; 476 (u8)TIM1_AutomaticOutput);
1405 021e 9f ld a,xl
1406 021f 1a01 or a,(OFST+1,sp)
1407 0221 1a06 or a,(OFST+6,sp)
1408 0223 1a07 or a,(OFST+7,sp)
1409 0225 1a08 or a,(OFST+8,sp)
1410 0227 c7526d ld 21101,a
1411 ; 478 }
1414 022a 85 popw x
1415 022b 81 ret
1617 ; 511 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
1617 ; 512 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
1617 ; 513 TIM1_ICSelection_TypeDef TIM1_ICSelection,
1617 ; 514 TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
1617 ; 515 u8 TIM1_ICFilter)
1617 ; 516 {
1618 switch .text
1619 022c _TIM1_ICInit:
1621 022c 89 pushw x
1622 00000000 OFST: set 0
1625 ; 519 assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
1627 ; 520 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
1629 ; 521 assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
1631 ; 522 assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
1633 ; 523 assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));
1635 ; 525 if (TIM1_Channel == TIM1_CHANNEL_1)
1637 022d 9e ld a,xh
1638 022e 4d tnz a
1639 022f 2614 jrne L766
1640 ; 528 TI1_Config(TIM1_ICPolarity,
1640 ; 529 TIM1_ICSelection,
1640 ; 530 TIM1_ICFilter);
1642 0231 7b07 ld a,(OFST+7,sp)
1643 0233 88 push a
1644 0234 7b06 ld a,(OFST+6,sp)
1645 0236 97 ld xl,a
1646 0237 7b03 ld a,(OFST+3,sp)
1647 0239 95 ld xh,a
1648 023a cd07a7 call L3_TI1_Config
1650 023d 84 pop a
1651 ; 532 TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
1653 023e 7b06 ld a,(OFST+6,sp)
1654 0240 cd0680 call _TIM1_SetIC1Prescaler
1657 0243 2044 jra L176
1658 0245 L766:
1659 ; 534 else if (TIM1_Channel == TIM1_CHANNEL_2)
1661 0245 7b01 ld a,(OFST+1,sp)
1662 0247 a101 cp a,#1
1663 0249 2614 jrne L376
1664 ; 537 TI2_Config(TIM1_ICPolarity,
1664 ; 538 TIM1_ICSelection,
1664 ; 539 TIM1_ICFilter);
1666 024b 7b07 ld a,(OFST+7,sp)
1667 024d 88 push a
1668 024e 7b06 ld a,(OFST+6,sp)
1669 0250 97 ld xl,a
1670 0251 7b03 ld a,(OFST+3,sp)
1671 0253 95 ld xh,a
1672 0254 cd07d7 call L5_TI2_Config
1674 0257 84 pop a
1675 ; 541 TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
1677 0258 7b06 ld a,(OFST+6,sp)
1678 025a cd068d call _TIM1_SetIC2Prescaler
1681 025d 202a jra L176
1682 025f L376:
1683 ; 543 else if (TIM1_Channel == TIM1_CHANNEL_3)
1685 025f a102 cp a,#2
1686 0261 2614 jrne L776
1687 ; 546 TI3_Config(TIM1_ICPolarity,
1687 ; 547 TIM1_ICSelection,
1687 ; 548 TIM1_ICFilter);
1689 0263 7b07 ld a,(OFST+7,sp)
1690 0265 88 push a
1691 0266 7b06 ld a,(OFST+6,sp)
1692 0268 97 ld xl,a
1693 0269 7b03 ld a,(OFST+3,sp)
1694 026b 95 ld xh,a
1695 026c cd0807 call L7_TI3_Config
1697 026f 84 pop a
1698 ; 550 TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
1700 0270 7b06 ld a,(OFST+6,sp)
1701 0272 cd069a call _TIM1_SetIC3Prescaler
1704 0275 2012 jra L176
1705 0277 L776:
1706 ; 555 TI4_Config(TIM1_ICPolarity,
1706 ; 556 TIM1_ICSelection,
1706 ; 557 TIM1_ICFilter);
1708 0277 7b07 ld a,(OFST+7,sp)
1709 0279 88 push a
1710 027a 7b06 ld a,(OFST+6,sp)
1711 027c 97 ld xl,a
1712 027d 7b03 ld a,(OFST+3,sp)
1713 027f 95 ld xh,a
1714 0280 cd0837 call L11_TI4_Config
1716 0283 84 pop a
1717 ; 559 TIM1_SetIC4Prescaler(TIM1_ICPrescaler);
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