📄 stm8s_uart1.ls
字号:
1763 ; 663 {
1764 switch .text
1765 0283 _UART1_SendBreak:
1769 ; 664 UART1->CR2 |= UART1_CR2_SBK;
1771 0283 72105235 bset 21045,#0
1772 ; 665 }
1775 0287 81 ret
1809 ; 685 void UART1_SetAddress(u8 UART1_Address)
1809 ; 686 {
1810 switch .text
1811 0288 _UART1_SetAddress:
1813 0288 88 push a
1814 00000000 OFST: set 0
1817 ; 688 assert_param(IS_UART1_ADDRESS_OK(UART1_Address));
1819 ; 691 UART1->CR4 &= ((u8)~UART1_CR4_ADD);
1821 0289 c65237 ld a,21047
1822 028c a4f0 and a,#240
1823 028e c75237 ld 21047,a
1824 ; 693 UART1->CR4 |= UART1_Address;
1826 0291 c65237 ld a,21047
1827 0294 1a01 or a,(OFST+1,sp)
1828 0296 c75237 ld 21047,a
1829 ; 694 }
1832 0299 84 pop a
1833 029a 81 ret
1867 ; 713 void UART1_SetGuardTime(u8 UART1_GuardTime)
1867 ; 714 {
1868 switch .text
1869 029b _UART1_SetGuardTime:
1873 ; 716 UART1->GTR = UART1_GuardTime;
1875 029b c75239 ld 21049,a
1876 ; 717 }
1879 029e 81 ret
1913 ; 751 void UART1_SetPrescaler(u8 UART1_Prescaler)
1913 ; 752 {
1914 switch .text
1915 029f _UART1_SetPrescaler:
1919 ; 754 UART1->PSCR = UART1_Prescaler;
1921 029f c7523a ld 21050,a
1922 ; 755 }
1925 02a2 81 ret
2068 ; 775 FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG)
2068 ; 776 {
2069 switch .text
2070 02a3 _UART1_GetFlagStatus:
2072 02a3 89 pushw x
2073 02a4 88 push a
2074 00000001 OFST: set 1
2077 ; 777 FlagStatus status = RESET;
2079 02a5 0f01 clr (OFST+0,sp)
2080 ; 780 assert_param(IS_UART1_FLAG_OK(UART1_FLAG));
2082 ; 784 if (UART1_FLAG == UART1_FLAG_LBDF)
2084 02a7 a30210 cpw x,#528
2085 02aa 2608 jrne L7501
2086 ; 786 if ((UART1->CR4 & (u8)UART1_FLAG) != (u8)0x00)
2088 02ac 9f ld a,xl
2089 02ad c45237 and a,21047
2090 02b0 271e jreq L5601
2091 ; 789 status = SET;
2093 02b2 2017 jp LC006
2094 ; 794 status = RESET;
2095 02b4 L7501:
2096 ; 797 else if (UART1_FLAG == UART1_FLAG_SBK)
2098 02b4 1e02 ldw x,(OFST+1,sp)
2099 02b6 a30101 cpw x,#257
2100 02b9 2609 jrne L7601
2101 ; 799 if ((UART1->CR2 & (u8)UART1_FLAG) != (u8)0x00)
2103 02bb c65235 ld a,21045
2104 02be 1503 bcp a,(OFST+2,sp)
2105 02c0 270d jreq L7701
2106 ; 802 status = SET;
2108 02c2 2007 jp LC006
2109 ; 807 status = RESET;
2110 02c4 L7601:
2111 ; 812 if ((UART1->SR & (u8)UART1_FLAG) != (u8)0x00)
2113 02c4 c65230 ld a,21040
2114 02c7 1503 bcp a,(OFST+2,sp)
2115 02c9 2704 jreq L7701
2116 ; 815 status = SET;
2118 02cb LC006:
2121 02cb a601 ld a,#1
2124 02cd 2001 jra L5601
2125 02cf L7701:
2126 ; 820 status = RESET;
2129 02cf 4f clr a
2130 02d0 L5601:
2131 ; 824 return status;
2135 02d0 5b03 addw sp,#3
2136 02d2 81 ret
2171 ; 859 void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG)
2171 ; 860 {
2172 switch .text
2173 02d3 _UART1_ClearFlag:
2177 ; 861 assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_FLAG));
2179 ; 864 if (UART1_FLAG == UART1_FLAG_RXNE)
2181 02d3 a30020 cpw x,#32
2182 02d6 2605 jrne L1211
2183 ; 866 UART1->SR = (u8)~(UART1_SR_RXNE);
2185 02d8 35df5230 mov 21040,#223
2188 02dc 81 ret
2189 02dd L1211:
2190 ; 871 UART1->CR4 &= (u8)~(UART1_CR4_LBDF);
2192 02dd 72195237 bres 21047,#4
2193 ; 873 }
2196 02e1 81 ret
2278 ; 900 ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT)
2278 ; 901 {
2279 switch .text
2280 02e2 _UART1_GetITStatus:
2282 02e2 89 pushw x
2283 02e3 89 pushw x
2284 00000002 OFST: set 2
2287 ; 902 ITStatus pendingbitstatus = RESET;
2289 ; 903 u8 itpos = 0;
2291 ; 904 u8 itmask1 = 0;
2293 ; 905 u8 itmask2 = 0;
2295 ; 906 u8 enablestatus = 0;
2297 ; 909 assert_param(IS_UART1_GET_IT_OK(UART1_IT));
2299 ; 912 itpos = (u8)((u8)1 << (u8)((u8)UART1_IT & (u8)0x0F));
2301 02e4 7b04 ld a,(OFST+2,sp)
2302 02e6 a40f and a,#15
2303 02e8 5f clrw x
2304 02e9 97 ld xl,a
2305 02ea a601 ld a,#1
2306 02ec 5d tnzw x
2307 02ed 2704 jreq L67
2308 02ef L001:
2309 02ef 48 sll a
2310 02f0 5a decw x
2311 02f1 26fc jrne L001
2312 02f3 L67:
2313 02f3 6b01 ld (OFST-1,sp),a
2314 ; 914 itmask1 = (u8)((u8)UART1_IT >> (u8)4);
2316 02f5 7b04 ld a,(OFST+2,sp)
2317 02f7 4e swap a
2318 02f8 a40f and a,#15
2319 02fa 6b02 ld (OFST+0,sp),a
2320 ; 916 itmask2 = (u8)((u8)1 << itmask1);
2322 02fc 5f clrw x
2323 02fd 97 ld xl,a
2324 02fe a601 ld a,#1
2325 0300 5d tnzw x
2326 0301 2704 jreq L201
2327 0303 L401:
2328 0303 48 sll a
2329 0304 5a decw x
2330 0305 26fc jrne L401
2331 0307 L201:
2332 0307 6b02 ld (OFST+0,sp),a
2333 ; 920 if (UART1_IT == UART1_IT_PE)
2335 0309 1e03 ldw x,(OFST+1,sp)
2336 030b a30100 cpw x,#256
2337 030e 260c jrne L7611
2338 ; 923 enablestatus = (u8)((u8)UART1->CR1 & itmask2);
2340 0310 c65234 ld a,21044
2341 0313 1402 and a,(OFST+0,sp)
2342 0315 6b02 ld (OFST+0,sp),a
2343 ; 926 if (((UART1->SR & itpos) != (u8)0x00) && enablestatus)
2345 0317 c65230 ld a,21040
2347 ; 929 pendingbitstatus = SET;
2349 031a 200f jp LC009
2350 ; 934 pendingbitstatus = RESET;
2351 031c L7611:
2352 ; 938 else if (UART1_IT == UART1_IT_LBDF)
2354 031c a30346 cpw x,#838
2355 031f 2616 jrne L7711
2356 ; 941 enablestatus = (u8)((u8)UART1->CR4 & itmask2);
2358 0321 c65237 ld a,21047
2359 0324 1402 and a,(OFST+0,sp)
2360 0326 6b02 ld (OFST+0,sp),a
2361 ; 943 if (((UART1->CR4 & itpos) != (u8)0x00) && enablestatus)
2363 0328 c65237 ld a,21047
2365 032b LC009:
2366 032b 1501 bcp a,(OFST-1,sp)
2367 032d 271a jreq L7021
2368 032f 7b02 ld a,(OFST+0,sp)
2369 0331 2716 jreq L7021
2370 ; 946 pendingbitstatus = SET;
2372 0333 LC008:
2375 0333 a601 ld a,#1
2377 0335 2013 jra L5711
2378 ; 951 pendingbitstatus = RESET;
2379 0337 L7711:
2380 ; 957 enablestatus = (u8)((u8)UART1->CR2 & itmask2);
2382 0337 c65235 ld a,21045
2383 033a 1402 and a,(OFST+0,sp)
2384 033c 6b02 ld (OFST+0,sp),a
2385 ; 959 if (((UART1->SR & itpos) != (u8)0x00) && enablestatus)
2387 033e c65230 ld a,21040
2388 0341 1501 bcp a,(OFST-1,sp)
2389 0343 2704 jreq L7021
2391 0345 7b02 ld a,(OFST+0,sp)
2392 ; 962 pendingbitstatus = SET;
2394 0347 26ea jrne LC008
2395 0349 L7021:
2396 ; 967 pendingbitstatus = RESET;
2400 0349 4f clr a
2401 034a L5711:
2402 ; 972 return pendingbitstatus;
2406 034a 5b04 addw sp,#4
2407 034c 81 ret
2443 ; 1006 void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT)
2443 ; 1007 {
2444 switch .text
2445 034d _UART1_ClearITPendingBit:
2449 ; 1008 assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_IT));
2451 ; 1011 if (UART1_IT == UART1_IT_RXNE)
2453 034d a30255 cpw x,#597
2454 0350 2605 jrne L1321
2455 ; 1013 UART1->SR = (u8)~(UART1_SR_RXNE);
2457 0352 35df5230 mov 21040,#223
2460 0356 81 ret
2461 0357 L1321:
2462 ; 1018 UART1->CR4 &= (u8)~(UART1_CR4_LBDF);
2464 0357 72195237 bres 21047,#4
2465 ; 1020 }
2468 035b 81 ret
2481 xref _CLK_GetClockFreq
2482 xdef _UART1_ClearITPendingBit
2483 xdef _UART1_GetITStatus
2484 xdef _UART1_ClearFlag
2485 xdef _UART1_GetFlagStatus
2486 xdef _UART1_SetPrescaler
2487 xdef _UART1_SetGuardTime
2488 xdef _UART1_SetAddress
2489 xdef _UART1_SendBreak
2490 xdef _UART1_SendData9
2491 xdef _UART1_SendData8
2492 xdef _UART1_ReceiveData9
2493 xdef _UART1_ReceiveData8
2494 xdef _UART1_ReceiverWakeUpCmd
2495 xdef _UART1_WakeUpConfig
2496 xdef _UART1_SmartCardNACKCmd
2497 xdef _UART1_SmartCardCmd
2498 xdef _UART1_LINCmd
2499 xdef _UART1_LINBreakDetectionConfig
2500 xdef _UART1_IrDACmd
2501 xdef _UART1_IrDAConfig
2502 xdef _UART1_HalfDuplexCmd
2503 xdef _UART1_ITConfig
2504 xdef _UART1_Cmd
2505 xdef _UART1_Init
2506 xdef _UART1_DeInit
2507 xref.b c_lreg
2508 xref.b c_x
2527 xref c_lursh
2528 xref c_lsub
2529 xref c_smul
2530 xref c_ludv
2531 xref c_rtol
2532 xref c_llsh
2533 xref c_ltor
2534 end
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