📄 stm8s_uart1.ls
字号:
874 ; 245 if (uartreg == 0x01)
876 018a 7b01 ld a,(OFST-1,sp)
877 018c a101 cp a,#1
878 018e 2607 jrne L723
879 ; 247 UART1->CR1 |= itpos;
881 0190 c65234 ld a,21044
882 0193 1a02 or a,(OFST+0,sp)
884 0195 201e jp LC002
885 0197 L723:
886 ; 249 else if (uartreg == 0x02)
888 0197 a102 cp a,#2
889 0199 2607 jrne L333
890 ; 251 UART1->CR2 |= itpos;
892 019b c65235 ld a,21045
893 019e 1a02 or a,(OFST+0,sp)
895 01a0 2022 jp LC003
896 01a2 L333:
897 ; 255 UART1->CR4 |= itpos;
899 01a2 c65237 ld a,21047
900 01a5 1a02 or a,(OFST+0,sp)
901 01a7 2026 jp LC001
902 01a9 L523:
903 ; 261 if (uartreg == 0x01)
905 01a9 7b01 ld a,(OFST-1,sp)
906 01ab a101 cp a,#1
907 01ad 260b jrne L143
908 ; 263 UART1->CR1 &= (u8)(~itpos);
910 01af 7b02 ld a,(OFST+0,sp)
911 01b1 43 cpl a
912 01b2 c45234 and a,21044
913 01b5 LC002:
914 01b5 c75234 ld 21044,a
916 01b8 2018 jra L733
917 01ba L143:
918 ; 265 else if (uartreg == 0x02)
920 01ba a102 cp a,#2
921 01bc 260b jrne L543
922 ; 267 UART1->CR2 &= (u8)(~itpos);
924 01be 7b02 ld a,(OFST+0,sp)
925 01c0 43 cpl a
926 01c1 c45235 and a,21045
927 01c4 LC003:
928 01c4 c75235 ld 21045,a
930 01c7 2009 jra L733
931 01c9 L543:
932 ; 271 UART1->CR4 &= (u8)(~itpos);
934 01c9 7b02 ld a,(OFST+0,sp)
935 01cb 43 cpl a
936 01cc c45237 and a,21047
937 01cf LC001:
938 01cf c75237 ld 21047,a
939 01d2 L733:
940 ; 275 }
943 01d2 5b04 addw sp,#4
944 01d4 81 ret
980 ; 292 void UART1_HalfDuplexCmd(FunctionalState NewState)
980 ; 293 {
981 switch .text
982 01d5 _UART1_HalfDuplexCmd:
986 ; 294 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
988 ; 296 if (NewState != DISABLE)
990 01d5 4d tnz a
991 01d6 2705 jreq L763
992 ; 298 UART1->CR5 |= UART1_CR5_HDSEL; /**< UART1 Half Duplex Enable */
994 01d8 72165238 bset 21048,#3
997 01dc 81 ret
998 01dd L763:
999 ; 302 UART1->CR5 &= (u8)~UART1_CR5_HDSEL; /**< UART1 Half Duplex Disable */
1001 01dd 72175238 bres 21048,#3
1002 ; 304 }
1005 01e1 81 ret
1062 ; 323 void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode)
1062 ; 324 {
1063 switch .text
1064 01e2 _UART1_IrDAConfig:
1068 ; 325 assert_param(IS_UART1_IRDAMODE_OK(UART1_IrDAMode));
1070 ; 327 if (UART1_IrDAMode != UART1_IRDAMODE_NORMAL)
1072 01e2 4d tnz a
1073 01e3 2705 jreq L124
1074 ; 329 UART1->CR5 |= UART1_CR5_IRLP;
1076 01e5 72145238 bset 21048,#2
1079 01e9 81 ret
1080 01ea L124:
1081 ; 333 UART1->CR5 &= ((u8)~UART1_CR5_IRLP);
1083 01ea 72155238 bres 21048,#2
1084 ; 335 }
1087 01ee 81 ret
1122 ; 354 void UART1_IrDACmd(FunctionalState NewState)
1122 ; 355 {
1123 switch .text
1124 01ef _UART1_IrDACmd:
1128 ; 358 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1130 ; 360 if (NewState != DISABLE)
1132 01ef 4d tnz a
1133 01f0 2705 jreq L344
1134 ; 363 UART1->CR5 |= UART1_CR5_IREN;
1136 01f2 72125238 bset 21048,#1
1139 01f6 81 ret
1140 01f7 L344:
1141 ; 368 UART1->CR5 &= ((u8)~UART1_CR5_IREN);
1143 01f7 72135238 bres 21048,#1
1144 ; 370 }
1147 01fb 81 ret
1206 ; 388 void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
1206 ; 389 {
1207 switch .text
1208 01fc _UART1_LINBreakDetectionConfig:
1212 ; 390 assert_param(IS_UART1_LINBREAKDETECTIONLENGTH_OK(UART1_LINBreakDetectionLength));
1214 ; 392 if (UART1_LINBreakDetectionLength != UART1_LINBREAKDETECTIONLENGTH_10BITS)
1216 01fc 4d tnz a
1217 01fd 2705 jreq L574
1218 ; 394 UART1->CR4 |= UART1_CR4_LBDL;
1220 01ff 721a5237 bset 21047,#5
1223 0203 81 ret
1224 0204 L574:
1225 ; 398 UART1->CR4 &= ((u8)~UART1_CR4_LBDL);
1227 0204 721b5237 bres 21047,#5
1228 ; 400 }
1231 0208 81 ret
1266 ; 418 void UART1_LINCmd(FunctionalState NewState)
1266 ; 419 {
1267 switch .text
1268 0209 _UART1_LINCmd:
1272 ; 420 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1274 ; 422 if (NewState != DISABLE)
1276 0209 4d tnz a
1277 020a 2705 jreq L715
1278 ; 425 UART1->CR3 |= UART1_CR3_LINEN;
1280 020c 721c5236 bset 21046,#6
1283 0210 81 ret
1284 0211 L715:
1285 ; 430 UART1->CR3 &= ((u8)~UART1_CR3_LINEN);
1287 0211 721d5236 bres 21046,#6
1288 ; 432 }
1291 0215 81 ret
1326 ; 451 void UART1_SmartCardCmd(FunctionalState NewState)
1326 ; 452 {
1327 switch .text
1328 0216 _UART1_SmartCardCmd:
1332 ; 453 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1334 ; 455 if (NewState != DISABLE)
1336 0216 4d tnz a
1337 0217 2705 jreq L145
1338 ; 458 UART1->CR5 |= UART1_CR5_SCEN;
1340 0219 721a5238 bset 21048,#5
1343 021d 81 ret
1344 021e L145:
1345 ; 463 UART1->CR5 &= ((u8)(~UART1_CR5_SCEN));
1347 021e 721b5238 bres 21048,#5
1348 ; 465 }
1351 0222 81 ret
1387 ; 485 void UART1_SmartCardNACKCmd(FunctionalState NewState)
1387 ; 486 {
1388 switch .text
1389 0223 _UART1_SmartCardNACKCmd:
1393 ; 487 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1395 ; 489 if (NewState != DISABLE)
1397 0223 4d tnz a
1398 0224 2705 jreq L365
1399 ; 492 UART1->CR5 |= UART1_CR5_NACK;
1401 0226 72185238 bset 21048,#4
1404 022a 81 ret
1405 022b L365:
1406 ; 497 UART1->CR5 &= ((u8)~(UART1_CR5_NACK));
1408 022b 72195238 bres 21048,#4
1409 ; 499 }
1412 022f 81 ret
1469 ; 518 void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp)
1469 ; 519 {
1470 switch .text
1471 0230 _UART1_WakeUpConfig:
1475 ; 520 assert_param(IS_UART1_WAKEUP_OK(UART1_WakeUp));
1477 ; 522 UART1->CR1 &= ((u8)~UART1_CR1_WAKE);
1479 0230 72175234 bres 21044,#3
1480 ; 523 UART1->CR1 |= (u8)UART1_WakeUp;
1482 0234 ca5234 or a,21044
1483 0237 c75234 ld 21044,a
1484 ; 524 }
1487 023a 81 ret
1523 ; 541 void UART1_ReceiverWakeUpCmd(FunctionalState NewState)
1523 ; 542 {
1524 switch .text
1525 023b _UART1_ReceiverWakeUpCmd:
1529 ; 543 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1531 ; 545 if (NewState != DISABLE)
1533 023b 4d tnz a
1534 023c 2705 jreq L336
1535 ; 548 UART1->CR2 |= UART1_CR2_RWU;
1537 023e 72125235 bset 21045,#1
1540 0242 81 ret
1541 0243 L336:
1542 ; 553 UART1->CR2 &= ((u8)~UART1_CR2_RWU);
1544 0243 72135235 bres 21045,#1
1545 ; 555 }
1548 0247 81 ret
1571 ; 572 u8 UART1_ReceiveData8(void)
1571 ; 573 {
1572 switch .text
1573 0248 _UART1_ReceiveData8:
1577 ; 574 return ((u8)UART1->DR);
1579 0248 c65231 ld a,21041
1582 024b 81 ret
1605 ; 593 u16 UART1_ReceiveData9(void)
1605 ; 594 {
1606 switch .text
1607 024c _UART1_ReceiveData9:
1609 024c 89 pushw x
1610 00000002 OFST: set 2
1613 ; 595 return (u16)( (((u16) UART1->DR) | ((u16)(((u16)( (u16)UART1->CR1 & (u16)UART1_CR1_R8)) << 1))) & ((u16)0x01FF));
1615 024d c65234 ld a,21044
1616 0250 a480 and a,#128
1617 0252 5f clrw x
1618 0253 02 rlwa x,a
1619 0254 58 sllw x
1620 0255 1f01 ldw (OFST-1,sp),x
1621 0257 5f clrw x
1622 0258 c65231 ld a,21041
1623 025b 97 ld xl,a
1624 025c 01 rrwa x,a
1625 025d 1a02 or a,(OFST+0,sp)
1626 025f 01 rrwa x,a
1627 0260 1a01 or a,(OFST-1,sp)
1628 0262 a401 and a,#1
1629 0264 01 rrwa x,a
1632 0265 5b02 addw sp,#2
1633 0267 81 ret
1667 ; 615 void UART1_SendData8(u8 Data)
1667 ; 616 {
1668 switch .text
1669 0268 _UART1_SendData8:
1673 ; 618 UART1->DR = Data;
1675 0268 c75231 ld 21041,a
1676 ; 619 }
1679 026b 81 ret
1713 ; 638 void UART1_SendData9(u16 Data)
1713 ; 639 {
1714 switch .text
1715 026c _UART1_SendData9:
1717 026c 89 pushw x
1718 00000000 OFST: set 0
1721 ; 641 UART1->CR1 &= ((u8)~UART1_CR1_T8);
1723 026d 721d5234 bres 21044,#6
1724 ; 643 UART1->CR1 |= (u8)(((u8)(Data >> 2)) & UART1_CR1_T8);
1726 0271 54 srlw x
1727 0272 54 srlw x
1728 0273 9f ld a,xl
1729 0274 a440 and a,#64
1730 0276 ca5234 or a,21044
1731 0279 c75234 ld 21044,a
1732 ; 645 UART1->DR = (u8)(Data);
1734 027c 7b02 ld a,(OFST+2,sp)
1735 027e c75231 ld 21041,a
1736 ; 646 }
1739 0281 85 popw x
1740 0282 81 ret
1763 ; 662 void UART1_SendBreak(void)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -