📄 stm8s_uart1.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Generator V4.2.8 - 03 Dec 2008
3 ; Optimizer V4.2.8 - 03 Dec 2008
44 ; 64 void UART1_DeInit(void)
44 ; 65 {
46 switch .text
47 0000 _UART1_DeInit:
49 0000 88 push a
50 00000001 OFST: set 1
53 ; 66 u8 dummy = 0;
55 0001 0f01 clr (OFST+0,sp)
56 ; 70 dummy = UART1->SR;
58 0003 c65230 ld a,21040
59 ; 71 dummy = UART1->DR;
61 0006 c65231 ld a,21041
62 ; 73 UART1->BRR2 = UART1_BRR2_RESET_VALUE; /*< Set UART1_BRR2 to reset value 0x00 */
64 0009 725f5233 clr 21043
65 ; 74 UART1->BRR1 = UART1_BRR1_RESET_VALUE; /*< Set UART1_BRR1 to reset value 0x00 */
67 000d 725f5232 clr 21042
68 ; 76 UART1->CR1 = UART1_CR1_RESET_VALUE; /*< Set UART1_CR1 to reset value 0x00 */
70 0011 725f5234 clr 21044
71 ; 77 UART1->CR2 = UART1_CR2_RESET_VALUE; /*< Set UART1_CR2 to reset value 0x00 */
73 0015 725f5235 clr 21045
74 ; 78 UART1->CR3 = UART1_CR3_RESET_VALUE; /*< Set UART1_CR3 to reset value 0x00 */
76 0019 725f5236 clr 21046
77 ; 79 UART1->CR4 = UART1_CR4_RESET_VALUE; /*< Set UART1_CR4 to reset value 0x00 */
79 001d 725f5237 clr 21047
80 ; 80 UART1->CR5 = UART1_CR5_RESET_VALUE; /*< Set UART1_CR5 to reset value 0x00 */
82 0021 725f5238 clr 21048
83 ; 82 UART1->GTR = UART1_GTR_RESET_VALUE;
85 0025 725f5239 clr 21049
86 ; 83 UART1->PSCR = UART1_PSCR_RESET_VALUE;
88 0029 725f523a clr 21050
89 ; 84 }
92 002d 84 pop a
93 002e 81 ret
396 .const: section .text
397 0000 L41:
398 0000 00000064 dc.l 100
399 ; 104 void UART1_Init(u32 BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
399 ; 105 {
400 switch .text
401 002f _UART1_Init:
403 002f 520c subw sp,#12
404 0000000c OFST: set 12
407 ; 106 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
409 0031 96 ldw x,sp
410 0032 1c0005 addw x,#OFST-7
411 0035 cd0000 call c_ltor
413 ; 109 assert_param(IS_UART1_BAUDRATE_OK(BaudRate));
415 ; 111 assert_param(IS_UART1_WORDLENGTH_OK(WordLength));
417 ; 113 assert_param(IS_UART1_STOPBITS_OK(StopBits));
419 ; 115 assert_param(IS_UART1_PARITY_OK(Parity));
421 ; 118 assert_param(IS_UART1_MODE_OK((u8)Mode));
423 ; 122 assert_param(IS_UART1_SYNCMODE_OK((u8)SyncMode));
425 ; 124 UART1->CR1 &= (u8)(~UART1_CR1_M); /**< Clear the word length bit */
427 0038 72195234 bres 21044,#4
428 ; 125 UART1->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART1_WordLength value */
430 003c c65234 ld a,21044
431 003f 1a13 or a,(OFST+7,sp)
432 0041 c75234 ld 21044,a
433 ; 127 UART1->CR3 &= (u8)(~UART1_CR3_STOP); /**< Clear the STOP bits */
435 0044 c65236 ld a,21046
436 0047 a4cf and a,#207
437 0049 c75236 ld 21046,a
438 ; 128 UART1->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART1_StopBits value */
440 004c c65236 ld a,21046
441 004f 1a14 or a,(OFST+8,sp)
442 0051 c75236 ld 21046,a
443 ; 130 UART1->CR1 &= (u8)(~(UART1_CR1_PCEN | UART1_CR1_PS )); /**< Clear the Parity Control bit */
445 0054 c65234 ld a,21044
446 0057 a4f9 and a,#249
447 0059 c75234 ld 21044,a
448 ; 131 UART1->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART1_Parity value */
450 005c c65234 ld a,21044
451 005f 1a15 or a,(OFST+9,sp)
452 0061 c75234 ld 21044,a
453 ; 133 UART1->BRR1 &= (u8)(~UART1_BRR1_DIVM); /**< Clear the LSB mantissa of UART1DIV */
455 0064 725f5232 clr 21042
456 ; 134 UART1->BRR2 &= (u8)(~UART1_BRR2_DIVM); /**< Clear the MSB mantissa of UART1DIV */
458 0068 c65233 ld a,21043
459 006b a40f and a,#15
460 006d c75233 ld 21043,a
461 ; 135 UART1->BRR2 &= (u8)(~UART1_BRR2_DIVF); /**< Clear the Fraction bits of UART1DIV */
463 0070 c65233 ld a,21043
464 0073 a4f0 and a,#240
465 0075 c75233 ld 21043,a
466 ; 138 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
468 0078 96 ldw x,sp
469 0079 1c000f addw x,#OFST+3
470 007c cd0000 call c_ltor
472 007f a604 ld a,#4
473 0081 cd0000 call c_llsh
475 0084 96 ldw x,sp
476 0085 5c incw x
477 0086 cd0000 call c_rtol
479 0089 cd0000 call _CLK_GetClockFreq
481 008c 96 ldw x,sp
482 008d 5c incw x
483 008e cd0000 call c_ludv
485 0091 96 ldw x,sp
486 0092 1c0009 addw x,#OFST-3
487 0095 cd0000 call c_rtol
489 ; 139 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
491 0098 96 ldw x,sp
492 0099 1c000f addw x,#OFST+3
493 009c cd0000 call c_ltor
495 009f a604 ld a,#4
496 00a1 cd0000 call c_llsh
498 00a4 96 ldw x,sp
499 00a5 5c incw x
500 00a6 cd0000 call c_rtol
502 00a9 cd0000 call _CLK_GetClockFreq
504 00ac a664 ld a,#100
505 00ae cd0000 call c_smul
507 00b1 96 ldw x,sp
508 00b2 5c incw x
509 00b3 cd0000 call c_ludv
511 00b6 96 ldw x,sp
512 00b7 1c0005 addw x,#OFST-7
513 00ba cd0000 call c_rtol
515 ; 140 UART1->BRR2 |= (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100)) << 4) / 100) & (u8)0x0F); /**< Set the fraction of UART1DIV */
517 00bd 96 ldw x,sp
518 00be 1c0009 addw x,#OFST-3
519 00c1 cd0000 call c_ltor
521 00c4 a664 ld a,#100
522 00c6 cd0000 call c_smul
524 00c9 96 ldw x,sp
525 00ca 5c incw x
526 00cb cd0000 call c_rtol
528 00ce 96 ldw x,sp
529 00cf 1c0005 addw x,#OFST-7
530 00d2 cd0000 call c_ltor
532 00d5 96 ldw x,sp
533 00d6 5c incw x
534 00d7 cd0000 call c_lsub
536 00da a604 ld a,#4
537 00dc cd0000 call c_llsh
539 00df ae0000 ldw x,#L41
540 00e2 cd0000 call c_ludv
542 00e5 b603 ld a,c_lreg+3
543 00e7 a40f and a,#15
544 00e9 ca5233 or a,21043
545 00ec c75233 ld 21043,a
546 ; 141 UART1->BRR2 |= (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0); /**< Set the MSB mantissa of UART1DIV */
548 00ef 96 ldw x,sp
549 00f0 1c0009 addw x,#OFST-3
550 00f3 cd0000 call c_ltor
552 00f6 a604 ld a,#4
553 00f8 cd0000 call c_lursh
555 00fb b603 ld a,c_lreg+3
556 00fd a4f0 and a,#240
557 00ff b703 ld c_lreg+3,a
558 0101 3f02 clr c_lreg+2
559 0103 3f01 clr c_lreg+1
560 0105 3f00 clr c_lreg
561 0107 ca5233 or a,21043
562 010a c75233 ld 21043,a
563 ; 142 UART1->BRR1 |= (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UART1DIV */
565 010d c65232 ld a,21042
566 0110 1a0c or a,(OFST+0,sp)
567 0112 c75232 ld 21042,a
568 ; 144 UART1->CR2 &= (u8)~(UART1_CR2_TEN | UART1_CR2_REN); /**< Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
570 0115 c65235 ld a,21045
571 0118 a4f3 and a,#243
572 011a c75235 ld 21045,a
573 ; 145 UART1->CR3 &= (u8)~(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL); /**< Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
575 011d c65236 ld a,21046
576 0120 a4f8 and a,#248
577 0122 c75236 ld 21046,a
578 ; 146 UART1->CR3 |= (u8)((u8)SyncMode & (u8)(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL)); /**< Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
580 0125 7b16 ld a,(OFST+10,sp)
581 0127 a407 and a,#7
582 0129 ca5236 or a,21046
583 012c c75236 ld 21046,a
584 ; 148 if ((u8)Mode & (u8)UART1_MODE_TX_ENABLE)
586 012f 7b17 ld a,(OFST+11,sp)
587 0131 a504 bcp a,#4
588 0133 2706 jreq L102
589 ; 150 UART1->CR2 |= (u8)UART1_CR2_TEN; /**< Set the Transmitter Enable bit */
591 0135 72165235 bset 21045,#3
593 0139 2004 jra L302
594 013b L102:
595 ; 154 UART1->CR2 &= (u8)(~UART1_CR2_TEN); /**< Clear the Transmitter Disable bit */
597 013b 72175235 bres 21045,#3
598 013f L302:
599 ; 156 if ((u8)Mode & (u8)UART1_MODE_RX_ENABLE)
601 013f a508 bcp a,#8
602 0141 2706 jreq L502
603 ; 158 UART1->CR2 |= (u8)UART1_CR2_REN; /**< Set the Receiver Enable bit */
605 0143 72145235 bset 21045,#2
607 0147 2004 jra L702
608 0149 L502:
609 ; 162 UART1->CR2 &= (u8)(~UART1_CR2_REN); /**< Clear the Receiver Disable bit */
611 0149 72155235 bres 21045,#2
612 014d L702:
613 ; 165 if ((u8)SyncMode&(u8)UART1_SYNCMODE_CLOCK_DISABLE)
615 014d 7b16 ld a,(OFST+10,sp)
616 014f 2a06 jrpl L112
617 ; 167 UART1->CR3 &= (u8)(~UART1_CR3_CKEN); /**< Clear the Clock Enable bit */
619 0151 72175236 bres 21046,#3
621 0155 2008 jra L312
622 0157 L112:
623 ; 172 UART1->CR3 |= (u8)((u8)SyncMode & UART1_CR3_CKEN);
625 0157 a408 and a,#8
626 0159 ca5236 or a,21046
627 015c c75236 ld 21046,a
628 015f L312:
629 ; 174 }
632 015f 5b0c addw sp,#12
633 0161 81 ret
688 ; 195 void UART1_Cmd(FunctionalState NewState)
688 ; 196 {
689 switch .text
690 0162 _UART1_Cmd:
694 ; 197 if (NewState != DISABLE)
696 0162 4d tnz a
697 0163 2705 jreq L342
698 ; 199 UART1->CR1 &= (u8)(~UART1_CR1_UARTD); /**< UART1 Enable */
700 0165 721b5234 bres 21044,#5
703 0169 81 ret
704 016a L342:
705 ; 203 UART1->CR1 |= UART1_CR1_UARTD; /**< UART1 Disable (for low power consumption) */
707 016a 721a5234 bset 21044,#5
708 ; 205 }
711 016e 81 ret
836 ; 231 void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
836 ; 232 {
837 switch .text
838 016f _UART1_ITConfig:
840 016f 89 pushw x
841 0170 89 pushw x
842 00000002 OFST: set 2
845 ; 233 u8 uartreg, itpos = 0x00;
847 ; 234 assert_param(IS_UART1_CONFIG_IT_OK(UART1_IT));
849 ; 235 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
851 ; 238 uartreg = (u8)(UART1_IT >> (u8)0x08);
853 0171 7b03 ld a,(OFST+1,sp)
854 0173 6b01 ld (OFST-1,sp),a
855 ; 240 itpos = (u8)((u8)1 << (u8)((u8)UART1_IT & (u8)0x0F));
857 0175 7b04 ld a,(OFST+2,sp)
858 0177 a40f and a,#15
859 0179 5f clrw x
860 017a 97 ld xl,a
861 017b a601 ld a,#1
862 017d 5d tnzw x
863 017e 2704 jreq L22
864 0180 L42:
865 0180 48 sll a
866 0181 5a decw x
867 0182 26fc jrne L42
868 0184 L22:
869 0184 6b02 ld (OFST+0,sp),a
870 ; 242 if (NewState != DISABLE)
872 0186 7b07 ld a,(OFST+5,sp)
873 0188 271f jreq L523
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