📄 stm8s_tim3.ls
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1030 ; 344 TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
1032 0127 7b08 ld a,(OFST+6,sp)
1033 0129 cd0282 call _TIM3_SetIC2Prescaler
1036 012c 2024 jra L724
1037 012e L524:
1038 ; 349 TI2_Config(TIM3_ICPolarity, TIM3_ICSelection,
1038 ; 350 TIM3_ICFilter);
1040 012e 7b09 ld a,(OFST+7,sp)
1041 0130 88 push a
1042 0131 7b08 ld a,(OFST+6,sp)
1043 0133 97 ld xl,a
1044 0134 7b05 ld a,(OFST+3,sp)
1045 0136 95 ld xh,a
1046 0137 cd0367 call L5_TI2_Config
1048 013a 84 pop a
1049 ; 353 TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
1051 013b 7b08 ld a,(OFST+6,sp)
1052 013d cd0282 call _TIM3_SetIC2Prescaler
1054 ; 356 TI1_Config(icpolarity, icselection, TIM3_ICFilter);
1056 0140 7b09 ld a,(OFST+7,sp)
1057 0142 88 push a
1058 0143 7b03 ld a,(OFST+1,sp)
1059 0145 97 ld xl,a
1060 0146 7b02 ld a,(OFST+0,sp)
1061 0148 95 ld xh,a
1062 0149 cd0337 call L3_TI1_Config
1064 014c 84 pop a
1065 ; 359 TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
1067 014d 7b08 ld a,(OFST+6,sp)
1068 014f cd0275 call _TIM3_SetIC1Prescaler
1070 0152 L724:
1071 ; 361 }
1074 0152 5b04 addw sp,#4
1075 0154 81 ret
1130 ; 379 void TIM3_Cmd(FunctionalState NewState)
1130 ; 380 {
1131 switch .text
1132 0155 _TIM3_Cmd:
1136 ; 382 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1138 ; 385 if (NewState != DISABLE)
1140 0155 4d tnz a
1141 0156 2705 jreq L754
1142 ; 387 TIM3->CR1 |= TIM3_CR1_CEN;
1144 0158 72105320 bset 21280,#0
1147 015c 81 ret
1148 015d L754:
1149 ; 391 TIM3->CR1 &= (u8)(~TIM3_CR1_CEN);
1151 015d 72115320 bres 21280,#0
1152 ; 393 }
1155 0161 81 ret
1227 ; 417 void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
1227 ; 418 {
1228 switch .text
1229 0162 _TIM3_ITConfig:
1231 0162 89 pushw x
1232 00000000 OFST: set 0
1235 ; 420 assert_param(IS_TIM3_IT_OK(TIM3_IT));
1237 ; 421 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1239 ; 423 if (NewState != DISABLE)
1241 0163 9f ld a,xl
1242 0164 4d tnz a
1243 0165 2706 jreq L715
1244 ; 426 TIM3->IER |= TIM3_IT;
1246 0167 9e ld a,xh
1247 0168 ca5321 or a,21281
1249 016b 2006 jra L125
1250 016d L715:
1251 ; 431 TIM3->IER &= (u8)(~TIM3_IT);
1253 016d 7b01 ld a,(OFST+1,sp)
1254 016f 43 cpl a
1255 0170 c45321 and a,21281
1256 0173 L125:
1257 0173 c75321 ld 21281,a
1258 ; 433 }
1261 0176 85 popw x
1262 0177 81 ret
1298 ; 451 void TIM3_UpdateDisableConfig(FunctionalState NewState)
1298 ; 452 {
1299 switch .text
1300 0178 _TIM3_UpdateDisableConfig:
1304 ; 454 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1306 ; 457 if (NewState != DISABLE)
1308 0178 4d tnz a
1309 0179 2705 jreq L145
1310 ; 459 TIM3->CR1 |= TIM3_CR1_UDIS;
1312 017b 72125320 bset 21280,#1
1315 017f 81 ret
1316 0180 L145:
1317 ; 463 TIM3->CR1 &= (u8)(~TIM3_CR1_UDIS);
1319 0180 72135320 bres 21280,#1
1320 ; 465 }
1323 0184 81 ret
1381 ; 484 void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
1381 ; 485 {
1382 switch .text
1383 0185 _TIM3_UpdateRequestConfig:
1387 ; 487 assert_param(IS_TIM3_UPDATE_SOURCE_OK(TIM3_UpdateSource));
1389 ; 490 if (TIM3_UpdateSource != TIM3_UPDATESOURCE_GLOBAL)
1391 0185 4d tnz a
1392 0186 2705 jreq L375
1393 ; 492 TIM3->CR1 |= TIM3_CR1_URS;
1395 0188 72145320 bset 21280,#2
1398 018c 81 ret
1399 018d L375:
1400 ; 496 TIM3->CR1 &= (u8)(~TIM3_CR1_URS);
1402 018d 72155320 bres 21280,#2
1403 ; 498 }
1406 0191 81 ret
1463 ; 518 void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)
1463 ; 519 {
1464 switch .text
1465 0192 _TIM3_SelectOnePulseMode:
1469 ; 521 assert_param(IS_TIM3_OPM_MODE_OK(TIM3_OPMode));
1471 ; 524 if (TIM3_OPMode != TIM3_OPMODE_REPETITIVE)
1473 0192 4d tnz a
1474 0193 2705 jreq L526
1475 ; 526 TIM3->CR1 |= TIM3_CR1_OPM;
1477 0195 72165320 bset 21280,#3
1480 0199 81 ret
1481 019a L526:
1482 ; 530 TIM3->CR1 &= (u8)(~TIM3_CR1_OPM);
1484 019a 72175320 bres 21280,#3
1485 ; 533 }
1488 019e 81 ret
1556 ; 573 void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
1556 ; 574 TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
1556 ; 575 {
1557 switch .text
1558 019f _TIM3_PrescalerConfig:
1562 ; 577 assert_param(IS_TIM3_PRESCALER_RELOAD_OK(TIM3_PSCReloadMode));
1564 ; 578 assert_param(IS_TIM3_PRESCALER_OK(Prescaler));
1566 ; 581 TIM3->PSCR = Prescaler;
1568 019f 9e ld a,xh
1569 01a0 c7532a ld 21290,a
1570 ; 584 TIM3->EGR = TIM3_PSCReloadMode;
1572 01a3 9f ld a,xl
1573 01a4 c75324 ld 21284,a
1574 ; 585 }
1577 01a7 81 ret
1635 ; 605 void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
1635 ; 606 {
1636 switch .text
1637 01a8 _TIM3_ForcedOC1Config:
1639 01a8 88 push a
1640 00000000 OFST: set 0
1643 ; 608 assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
1645 ; 611 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
1647 01a9 c65325 ld a,21285
1648 01ac a48f and a,#143
1649 01ae 1a01 or a,(OFST+1,sp)
1650 01b0 c75325 ld 21285,a
1651 ; 612 }
1654 01b3 84 pop a
1655 01b4 81 ret
1691 ; 632 void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
1691 ; 633 {
1692 switch .text
1693 01b5 _TIM3_ForcedOC2Config:
1695 01b5 88 push a
1696 00000000 OFST: set 0
1699 ; 635 assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
1701 ; 638 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
1703 01b6 c65326 ld a,21286
1704 01b9 a48f and a,#143
1705 01bb 1a01 or a,(OFST+1,sp)
1706 01bd c75326 ld 21286,a
1707 ; 639 }
1710 01c0 84 pop a
1711 01c1 81 ret
1747 ; 657 void TIM3_ARRPreloadConfig(FunctionalState NewState)
1747 ; 658 {
1748 switch .text
1749 01c2 _TIM3_ARRPreloadConfig:
1753 ; 660 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1755 ; 663 if (NewState != DISABLE)
1757 01c2 4d tnz a
1758 01c3 2705 jreq L547
1759 ; 665 TIM3->CR1 |= TIM3_CR1_ARPE;
1761 01c5 721e5320 bset 21280,#7
1764 01c9 81 ret
1765 01ca L547:
1766 ; 669 TIM3->CR1 &= (u8)(~TIM3_CR1_ARPE);
1768 01ca 721f5320 bres 21280,#7
1769 ; 671 }
1772 01ce 81 ret
1808 ; 689 void TIM3_OC1PreloadConfig(FunctionalState NewState)
1808 ; 690 {
1809 switch .text
1810 01cf _TIM3_OC1PreloadConfig:
1814 ; 692 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1816 ; 695 if (NewState != DISABLE)
1818 01cf 4d tnz a
1819 01d0 2705 jreq L767
1820 ; 697 TIM3->CCMR1 |= TIM3_CCMR_OCxPE;
1822 01d2 72165325 bset 21285,#3
1825 01d6 81 ret
1826 01d7 L767:
1827 ; 701 TIM3->CCMR1 &= (u8)(~TIM3_CCMR_OCxPE);
1829 01d7 72175325 bres 21285,#3
1830 ; 703 }
1833 01db 81 ret
1869 ; 721 void TIM3_OC2PreloadConfig(FunctionalState NewState)
1869 ; 722 {
1870 switch .text
1871 01dc _TIM3_OC2PreloadConfig:
1875 ; 724 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1877 ; 727 if (NewState != DISABLE)
1879 01dc 4d tnz a
1880 01dd 2705 jreq L1101
1881 ; 729 TIM3->CCMR2 |= TIM3_CCMR_OCxPE;
1883 01df 72165326 bset 21286,#3
1886 01e3 81 ret
1887 01e4 L1101:
1888 ; 733 TIM3->CCMR2 &= (u8)(~TIM3_CCMR_OCxPE);
1890 01e4 72175326 bres 21286,#3
1891 ; 735 }
1894 01e8 81 ret
1959 ; 755 void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)
1959 ; 756 {
1960 switch .text
1961 01e9 _TIM3_GenerateEvent:
1965 ; 758 assert_param(IS_TIM3_EVENT_SOURCE_OK(TIM3_EventSource));
1967 ; 761 TIM3->EGR = TIM3_EventSource;
1969 01e9 c75324 ld 21284,a
1970 ; 762 }
1973 01ec 81 ret
2009 ; 782 void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
2009 ; 783 {
2010 switch .text
2011 01ed _TIM3_OC1PolarityConfig:
2015 ; 785 assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
2017 ; 788 if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
2019 01ed 4d tnz a
2020 01ee 2705 jreq L3601
2021 ; 790 TIM3->CCER1 |= TIM3_CCER1_CC1P;
2023 01f0 72125327 bset 21287,#1
2026 01f4 81 ret
2027 01f5 L3601:
2028 ; 794 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1P);
2030 01f5 72135327 bres 21287,#1
2031 ; 796 }
2034 01f9 81 ret
2070 ; 816 void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
2070 ; 817 {
2071 switch .text
2072 01fa _TIM3_OC2PolarityConfig:
2076 ; 819 assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
2078 ; 822 if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
2080 01fa 4d tnz a
2081 01fb 2705 jreq L5011
2082 ; 824 TIM3->CCER1 |= TIM3_CCER1_CC2P;
2084 01fd 721a5327 bset 21287,#5
2087 0201 81 ret
2088 0202 L5011:
2089 ; 828 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2P);
2091 0202 721b5327 bres 21287,#5
2092 ; 830 }
2095 0206 81 ret
2140 ; 852 void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
2140 ; 853 {
2141 switch .text
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