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📄 stm8s_spi.ls

📁 STM8-触摸例程
💻 LS
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字号:
   1                     ; C Compiler for STM8 (COSMIC Software)
   2                     ; Generator V4.2.8 - 03 Dec 2008
   3                     ; Optimizer V4.2.8 - 03 Dec 2008
  33                     ; 61 void SPI_DeInit(void)
  33                     ; 62 {
  35                     	switch	.text
  36  0000               _SPI_DeInit:
  40                     ; 63   SPI->CR1    = SPI_CR1_RESET_VALUE;
  42  0000 725f5200      	clr	20992
  43                     ; 64   SPI->CR2    = SPI_CR2_RESET_VALUE;
  45  0004 725f5201      	clr	20993
  46                     ; 65   SPI->ICR    = SPI_ICR_RESET_VALUE;
  48  0008 725f5202      	clr	20994
  49                     ; 66   SPI->SR     = SPI_SR_RESET_VALUE;
  51  000c 35025203      	mov	20995,#2
  52                     ; 67   SPI->CRCPR  = SPI_CRCPR_RESET_VALUE;
  54  0010 35075205      	mov	20997,#7
  55                     ; 68 }
  58  0014 81            	ret	
 374                     ; 90 void SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, u8 CRCPolynomial)
 374                     ; 91 {
 375                     	switch	.text
 376  0015               _SPI_Init:
 378  0015 89            	pushw	x
 379       00000000      OFST:	set	0
 382                     ; 93   assert_param(IS_SPI_FIRSTBIT_OK(FirstBit));
 384                     ; 94   assert_param(IS_SPI_BAUDRATE_PRESCALER_OK(BaudRatePrescaler));
 386                     ; 95   assert_param(IS_SPI_MODE_OK(Mode));
 388                     ; 96   assert_param(IS_SPI_POLARITY_OK(ClockPolarity));
 390                     ; 97   assert_param(IS_SPI_PHASE_OK(ClockPhase));
 392                     ; 98   assert_param(IS_SPI_DATA_DIRECTION_OK(Data_Direction));
 394                     ; 99   assert_param(IS_SPI_SLAVEMANAGEMENT_OK(Slave_Management));
 396                     ; 100   assert_param(IS_SPI_CRC_POLYNOMIAL_OK(CRCPolynomial));
 398                     ; 103   SPI->CR1 = (u8)((u8)(FirstBit) |
 398                     ; 104                   (u8)(BaudRatePrescaler) |
 398                     ; 105                   (u8)(ClockPolarity) |
 398                     ; 106                   (u8)(ClockPhase));
 400  0016 9f            	ld	a,xl
 401  0017 1a01          	or	a,(OFST+1,sp)
 402  0019 1a06          	or	a,(OFST+6,sp)
 403  001b 1a07          	or	a,(OFST+7,sp)
 404  001d c75200        	ld	20992,a
 405                     ; 109   SPI->CR2 = (u8)((u8)(Data_Direction) | (u8)(Slave_Management));
 407  0020 7b08          	ld	a,(OFST+8,sp)
 408  0022 1a09          	or	a,(OFST+9,sp)
 409  0024 c75201        	ld	20993,a
 410                     ; 111   if (Mode == SPI_MODE_MASTER)
 412  0027 7b05          	ld	a,(OFST+5,sp)
 413  0029 a104          	cp	a,#4
 414  002b 2606          	jrne	L302
 415                     ; 113     SPI->CR2 |= (u8)SPI_CR2_SSI;
 417  002d 72105201      	bset	20993,#0
 419  0031 2004          	jra	L502
 420  0033               L302:
 421                     ; 117     SPI->CR2 &= (u8)~(SPI_CR2_SSI);
 423  0033 72115201      	bres	20993,#0
 424  0037               L502:
 425                     ; 121   SPI->CR1 |= (u8)(Mode);
 427  0037 c65200        	ld	a,20992
 428  003a 1a05          	or	a,(OFST+5,sp)
 429  003c c75200        	ld	20992,a
 430                     ; 124   SPI->CRCPR = (u8)CRCPolynomial;
 432  003f 7b0a          	ld	a,(OFST+10,sp)
 433  0041 c75205        	ld	20997,a
 434                     ; 125 }
 437  0044 85            	popw	x
 438  0045 81            	ret	
 493                     ; 143 void SPI_Cmd(FunctionalState NewState)
 493                     ; 144 {
 494                     	switch	.text
 495  0046               _SPI_Cmd:
 499                     ; 146   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
 501                     ; 148   if (NewState != DISABLE)
 503  0046 4d            	tnz	a
 504  0047 2705          	jreq	L532
 505                     ; 150     SPI->CR1 |= SPI_CR1_SPE; /* Enable the SPI peripheral*/
 507  0049 721c5200      	bset	20992,#6
 510  004d 81            	ret	
 511  004e               L532:
 512                     ; 154     SPI->CR1 &= (u8)(~SPI_CR1_SPE); /* Disable the SPI peripheral*/
 514  004e 721d5200      	bres	20992,#6
 515                     ; 156 }
 518  0052 81            	ret	
 627                     ; 174 void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
 627                     ; 175 {
 628                     	switch	.text
 629  0053               _SPI_ITConfig:
 631  0053 89            	pushw	x
 632  0054 88            	push	a
 633       00000001      OFST:	set	1
 636                     ; 176   u8 itpos = 0;
 638  0055 0f01          	clr	(OFST+0,sp)
 639                     ; 178   assert_param(IS_SPI_CONFIG_IT_OK(SPI_IT));
 641                     ; 179   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
 643                     ; 182   itpos = (u8)((u8)1 << (u8)((u8)SPI_IT & (u8)0x0F));
 645  0057 9e            	ld	a,xh
 646  0058 a40f          	and	a,#15
 647  005a 5f            	clrw	x
 648  005b 97            	ld	xl,a
 649  005c a601          	ld	a,#1
 650  005e 5d            	tnzw	x
 651  005f 2704          	jreq	L41
 652  0061               L61:
 653  0061 48            	sll	a
 654  0062 5a            	decw	x
 655  0063 26fc          	jrne	L61
 656  0065               L41:
 657  0065 6b01          	ld	(OFST+0,sp),a
 658                     ; 184   if (NewState != DISABLE)
 660  0067 0d03          	tnz	(OFST+2,sp)
 661  0069 2707          	jreq	L113
 662                     ; 186     SPI->ICR |= itpos; /* Enable interrupt*/
 664  006b c65202        	ld	a,20994
 665  006e 1a01          	or	a,(OFST+0,sp)
 667  0070 2004          	jra	L313
 668  0072               L113:
 669                     ; 190     SPI->ICR &= (u8)(~itpos); /* Disable interrupt*/
 671  0072 43            	cpl	a
 672  0073 c45202        	and	a,20994
 673  0076               L313:
 674  0076 c75202        	ld	20994,a
 675                     ; 192 }
 678  0079 5b03          	addw	sp,#3
 679  007b 81            	ret	
 713                     ; 206 void SPI_SendData(u8 Data)
 713                     ; 207 {
 714                     	switch	.text
 715  007c               _SPI_SendData:
 719                     ; 208   SPI->DR = Data; /* Write in the DR register the data to be sent*/
 721  007c c75204        	ld	20996,a
 722                     ; 209 }
 725  007f 81            	ret	
 748                     ; 225 u8 SPI_ReceiveData(void)
 748                     ; 226 {
 749                     	switch	.text
 750  0080               _SPI_ReceiveData:
 754                     ; 227   return ((u8)SPI->DR); /* Return the data in the DR register*/
 756  0080 c65204        	ld	a,20996
 759  0083 81            	ret	
 795                     ; 246 void SPI_NSSInternalSoftwareCmd(FunctionalState NewState)
 795                     ; 247 {
 796                     	switch	.text
 797  0084               _SPI_NSSInternalSoftwareCmd:
 801                     ; 249   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
 803                     ; 251   if (NewState != DISABLE)
 805  0084 4d            	tnz	a
 806  0085 2705          	jreq	L163
 807                     ; 253     SPI->CR2 |= SPI_CR2_SSI; /* Set NSS pin internally by software*/
 809  0087 72105201      	bset	20993,#0
 812  008b 81            	ret	
 813  008c               L163:
 814                     ; 257     SPI->CR2 &= (u8)(~SPI_CR2_SSI); /* Reset NSS pin internally by software*/
 816  008c 72115201      	bres	20993,#0
 817                     ; 259 }
 820  0090 81            	ret	
 843                     ; 275 void SPI_TransmitCRC(void)
 843                     ; 276 {
 844                     	switch	.text
 845  0091               _SPI_TransmitCRC:
 849                     ; 277   SPI->CR2 |= SPI_CR2_CRCNEXT; /* Enable the CRC transmission*/
 851  0091 72185201      	bset	20993,#4
 852                     ; 278 }
 855  0095 81            	ret	
 892                     ; 295 void SPI_CalculateCRCCmd(FunctionalState NewState)
 892                     ; 296 {
 893                     	switch	.text
 894  0096               _SPI_CalculateCRCCmd:
 896  0096 88            	push	a
 897       00000000      OFST:	set	0
 900                     ; 298   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
 902                     ; 301   SPI_Cmd(DISABLE);
 904  0097 4f            	clr	a
 905  0098 adac          	call	_SPI_Cmd
 907                     ; 303   if (NewState != DISABLE)
 909  009a 7b01          	ld	a,(OFST+1,sp)
 910  009c 2706          	jreq	L314
 911                     ; 305     SPI->CR2 |= SPI_CR2_CRCEN; /* Enable the CRC calculation*/
 913  009e 721a5201      	bset	20993,#5
 915  00a2 2004          	jra	L514
 916  00a4               L314:
 917                     ; 309     SPI->CR2 &= (u8)(~SPI_CR2_CRCEN); /* Disable the CRC calculation*/
 919  00a4 721b5201      	bres	20993,#5
 920  00a8               L514:
 921                     ; 311 }
 924  00a8 84            	pop	a
 925  00a9 81            	ret	
 989                     ; 326 u8 SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC)
 989                     ; 327 {
 990                     	switch	.text
 991  00aa               _SPI_GetCRC:

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